Abstract: The present disclosure provides a method for topography simulation of a physical structure under a topography-changing process. The method includes initializing a voxel mesh as a three-dimensional (3D) representation of the physical structure, generating a batch of particles, simulating a flight path of one of the particles with a ray-tracing method by a parallel processing thread in a hardware accelerator, identifying a surface normal of a voxel unit in the voxel mesh that intersects the flight path by the parallel processing thread, determining a surface reaction between the one of the particles and the voxel unit by a central processing unit (CPU), and updating the voxel mesh based on the determining of the surface reaction.

Abstract: A method of manufacturing a semiconductor device, a plurality of fin structures are formed over a semiconductor substrate. The fin structures extend along a first direction and are arranged in a second direction crossing the first direction. A plurality of sacrificial gate structures extending in the second direction are formed over the fin structures. An interlayer dielectric layer is formed over the plurality of fin structures between adjacent sacrificial gate structures. The sacrificial gate structures are cut into a plurality of pieces of sacrificial gate structures by forming gate end spaces along the second direction. Gate separation plugs are formed by filling the gate end spaces with two or more dielectric materials. The two or more dielectric materials includes a first layer and a second layer formed on the first layer, and a dielectric constant of the second layer is smaller than a dielectric constant of the first layer.

Abstract: The present disclosure provides embodiments of semiconductor devices. In one embodiment, the semiconductor device includes a dielectric layer and a fin-shaped structure disposed over the dielectric layer. The fin-shaped structure includes a first p-type doped region, a second p-type doped region, and a third p-type doped region, and a first n-type doped region, a second n-type doped region, and a third n-type doped region interleaving the first p-type doped region, the second p-type doped region, and the third p-type doped region. The first p-type doped region, the third p-type doped region and the third n-type doped region are electrically coupled to a first potential. The second p-type doped region, the first n-type doped region and the second n-type doped region are electrically coupled to a second potential different from the first potential.

Abstract: A semiconductor device structure, along with methods of forming such, are described. In one embodiment, a semiconductor device structure is provided. The semiconductor device structure includes a substrate having a front side and a back side opposing the front side, a gate stack disposed on the front side of the substrate, and a first source/drain feature and a second source/drain feature disposed in opposing sides of the gate stack. Each first source/drain feature and second source/drain feature comprises a first side and a second side, and a portion of the back side of the substrate is exposed to an air gap.

Abstract: The present disclosure provides a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes channel members vertically stacked above a substrate, a gate structure engaging the channel members, a gate sidewall spacer disposed on a sidewall of the gate structure, an epitaxial feature abutting end portions of the channel members, and inner spacers interposing the gate structure and the epitaxial feature. The end portion of at least one of the channel members includes a first dopant. A concentration of the first dopant in the end portion of the at least one of the channel members is higher than in a center portion of the at least one of the channel members. The concentration of the first dopant in the end portion of the at least one of the channel members is higher than in an outer portion of the epitaxial feature.

Abstract: Embodiments of the present disclosure provide a semiconductor device structure including a first channel layer formed of a first material, wherein the first channel layer has a first width, a second channel layer formed of a second material different from the first material, wherein the second channel layer has a second width less than the first width, and the second channel layer is in contact with a first surface of the first channel layer. The structure also includes a third channel layer formed of the second material, wherein the third channel layer has a third width less than the second width, and the third channel layer is in contact with a second surface of the first channel layer. The structure also includes a gate dielectric layer conformally disposed on the first channel layer, the second channel layer, and the third channel layer, and a gate electrode layer disposed on the gate dielectric layer.

Abstract: A method of manufacturing a semiconductor device, a plurality of fin structures are formed over a semiconductor substrate. The fin structures extend along a first direction and are arranged in a second direction crossing the first direction. A plurality of sacrificial gate structures extending in the second direction are formed over the fin structures. An interlayer dielectric layer is formed over the plurality of fin structures between adjacent sacrificial gate structures. The sacrificial gate structures are cut into a plurality of pieces of sacrificial gate structures by forming gate end spaces along the second direction. Gate separation plugs are formed by filling the gate end spaces with two or more dielectric materials. The two or more dielectric materials includes a first layer and a second layer formed on the first layer, and a dielectric constant of the second layer is smaller than a dielectric constant of the first layer.

Abstract: A semiconductor device includes semiconductor channel members disposed over a substrate, a gate dielectric layer disposed on and wrapping around the semiconductor channel members, a gate electrode layer disposed on the gate dielectric layer and wrapping around the semiconductor channel members, a source/drain (S/D) epitaxial layer in physical contact with the semiconductor channel members, and a dielectric spacer interposing the S/D epitaxial layer and the gate dielectric layer. The dielectric spacer includes a first dielectric layer in physical contact with the gate dielectric layer and a second dielectric layer in physical contact with the first dielectric layer. The first dielectric layer has a dielectric constant higher than that of the second dielectric layer. The second dielectric layer separates the first dielectric layer from physically contacting the S/D epitaxial layer.

Abstract: A method of generating an IC layout diagram includes receiving an IC layout diagram including a gate region and a gate via, the gate via being positioned at a location within an active region and along a width of the gate region extending across the active region, receiving a first gate resistance value of the gate region, retrieving a second gate resistance value from a resistance value reference based on the location and the width, using the first and second resistance values to determine that the IC layout diagram does not comply with a design specification, and based on the non-compliance with the design specification, modifying the IC layout diagram.

Abstract: The present disclosure provides a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes channel members disposed over a substrate, a gate structure engaging the channel members, and an epitaxial feature adjacent the channel members. At least one of the channel members has an end portion in physical contact with an outer portion of the epitaxial feature. The end portion of the at least one of the channel members includes a first dopant of a first concentration. The outer portion of the epitaxial feature includes a second dopant of a second concentration. The first concentration is higher than the second concentration.

Abstract: A semiconductor device includes first nanostructures vertically separated from one another, a first gate structure wrapping around each of the first nanostructures, and second nanostructures vertically separated from one another. The semiconductor device also includes a second gate structure wrapping around the second nanostructures, a first drain/source structure coupled to a first end of the first nanostructures, a second drain/source structure coupled to both of a second end of the first nanostructures and a first end of the second nanostructures, and a third drain/source structure coupled to a second end of the second nanostructures. The first drain/source structure has a first doping type, the second and third drain/source structures have a second doping type, and the first doping type is opposite to the second doping type.

Abstract: Embodiments of the present disclosure provide a method for forming semiconductor device structures. The method includes forming a fin structure having a stack of semiconductor layers comprising first semiconductor layers and second semiconductor layers alternatingly arranged, forming a sacrificial gate structure over a portion of the fin structure, removing the first and second semiconductor layers in a source/drain region of the fin structure that is not covered by the sacrificial gate structure, forming an epitaxial source/drain feature in the source/drain region, removing portions of the sacrificial gate structure to expose the first and second semiconductor layers, removing portions of the second semiconductor layers so that at least one second semiconductor layer has a width less than a width of each of the first semiconductor layers, forming a conformal gate dielectric layer on exposed first and second semiconductor layers, and forming a gate electrode layer on the conformal gate dielectric layer.

Abstract: A method of manufacturing a semiconductor device includes forming a fin structure in which first semiconductor layers and second semiconductor layers are alternatively stacked; forming a sacrificial gate structure over the fin structure; etching a source/drain (S/D) region of the fin structure, which is not covered by the sacrificial gate structure, thereby forming an S/D space; laterally etching the first semiconductor layers through the S/D space, thereby forming recesses; forming a first insulating layer, in the recesses, on the etched first semiconductor layers; after the first insulating layer is formed, forming a second insulating layer, in the recesses, on the first insulating layer, wherein a dielectric constant of the second insulating layer is less than that of the first insulating layer; and forming an S/D epitaxial layer in the S/D space, wherein the second insulating layer is in contact with the S/D epitaxial layer.

Abstract: A method of generating an IC layout diagram includes receiving a first gate resistance value of a gate region in an IC layout diagram, the first gate resistance value corresponding to a location of a gate via positioned within an active region and along a width of the gate region extending across the active region, determining a second gate resistance value based on the location and the width, using the first and second resistance values to determine that the IC layout diagram does not comply with a design specification, and based on the non-compliance with the design specification, modifying the IC layout diagram.

Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a substrate. The method includes forming a nanostructure stack over the substrate. The method includes forming a gate stack over the nanostructure stack and the substrate. The method includes removing the first nanostructure forming a first gap between the substrate and the second nanostructure. The method includes forming a first spacer layer in the first gap and a gate spacer over a sidewall of the gate stack. The method includes partially removing the nanostructure stack, which is not covered by the gate stack and the gate spacer, to form a first trench in the nanostructure stack. The method includes forming a source/drain structure in the first trench and over the first spacer layer.

Abstract: A semiconductor device includes first nanostructures vertically separated from one another, a first gate structure wrapping around each of the first nanostructures, and second nanostructures vertically separated from one another. The semiconductor device also includes a second gate structure wrapping around the second nanostructures, a first drain/source structure coupled to a first end of the first nanostructures, a second drain/source structure coupled to both of a second end of the first nanostructures and a first end of the second nanostructures, and a third drain/source structure coupled to a second end of the second nanostructures. The first drain/source structure has a first doping type, the second and third drain/source structures have a second doping type, and the first doping type is opposite to the second doping type.

Abstract: The present disclosure provides a method for topography simulation of a physical structure under a topography-changing process. The method includes initializing a voxel mesh as a three-dimensional (3D) representation of the physical structure, generating a batch of particles, simulating a flight path of one of the particles with a ray-tracing method by a parallel processing thread in a hardware accelerator, identifying a surface normal of a voxel unit in the voxel mesh that intersects the flight path by the parallel processing thread, determining a surface reaction between the one of the particles and the voxel unit by a central processing unit (CPU), and updating the voxel mesh based on the determining of the surface reaction.

Abstract: The present disclosure provides a method for topography simulation of a physical structure under a topography-changing process. The method includes initializing a voxel mesh as a three-dimensional (3D) representation of the physical structure, generating a batch of particles, simulating a flight path of at least one of the particles with a ray-tracing method, identifying a voxel unit in the voxel mesh that intersects the flight path, determining a surface reaction between the one of the particles and the voxel unit, and adding an extra voxel unit adjacent to the voxel unit based on the determining of the surface reaction.

Abstract: A method includes receiving a semiconductor substrate. The semiconductor substrate has a top surface and includes a semiconductor element. Moreover, the semiconductor substrate has a fin structure formed thereon. The method also includes recessing the fin structure to form source/drain trenches, forming a first dielectric layer over the recessed fin structure in the source/drain trenches, implanting a dopant element into a portion of the fin structure beneath a bottom surface of the source/drain trenches to form an amorphous semiconductor layer, forming a second dielectric layer over the recessed fin structure in the source/drain trenches, annealing the semiconductor substrate, and removing the first and second dielectric layers. After the annealing and the removing steps, the method further includes further recessing the recessed fin structure to provide a top surface. Additionally, the method includes forming an epitaxial layer from and on the top surface.

Abstract: Source/drain silicide that improves performance and methods for fabricating such are disclosed herein. An exemplary device includes a first channel layer disposed over a substrate, a second channel layer disposed over the first channel layer, and a gate stack that surrounds the first channel layer and the second channel layer. A source/drain feature disposed adjacent the first channel layer, second channel layer, and gate stack. The source/drain feature is disposed over first facets of the first channel layer and second facets of the second channel layer. The first facets and the second facets have a (111) crystallographic orientation. An inner spacer disposed between the gate stack and the source/drain feature and between the first channel layer and the second channel layer. A silicide feature is disposed over the source/drain feature where the silicide feature extends into the source/drain feature towards the substrate to a depth of the first channel layer.