Patents by Inventor Wen-Hsing Hsieh
Wen-Hsing Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9887269Abstract: A semiconductor device includes a source/drain feature disposed over a substrate. The source/drain feature includes a first nanowire, a second nanowire disposed over the first nanowire, a cladding layer disposed over the first nanowire and the second nanowire and a spacer layer extending from the first nanowire to the second nanowire. The device also includes a conductive feature disposed directly on the source/drain feature such that the conductive feature physically contacts the cladding layer and the spacer layer.Type: GrantFiled: November 30, 2015Date of Patent: February 6, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kuo-Cheng Ching, Ching-Fang Huang, Carlos H. Diaz, Chih-Hao Wang, Wen-Hsing Hsieh, Ying-Keung Leung
-
Publication number: 20170358500Abstract: Various semiconductor devices, such as horizontal gate-all-around devices, and methods of fabricating such are disclosed herein. An exemplary semiconductor device includes a fin structure having a channel region disposed between a first source/drain region and a second source/drain region. The fin structure includes a first nanowire and a second nanowire disposed in the channel region, the first source/drain region, and the second source/drain region. The fin structure further includes an epitaxial layer that wraps the first nanowire and the second nanowire in the first source/drain region and the second source/drain region. A gate is disposed over the channel region of the fin structure, such that the gate wraps the first nanowire and the second nanowire in the channel region. In some implementations, the first nanowire, the second nanowire, and the epitaxial layer combine to have a vertical bar-like shape in the first source/drain region and the second source/drain region.Type: ApplicationFiled: August 7, 2017Publication date: December 14, 2017Inventors: Chun-Hsiung Lin, Chung-Cheng Wu, Carlos H. Diaz, Chih-Hao Wang, Wen-Hsing Hsieh, Yi-Ming Sheu
-
Publication number: 20170309707Abstract: A semiconductor device includes a substrate, a first source/drain (S/D) region, a second S/D region, and a semiconductor sheet. The first S/D region is disposed on the substrate. The second S/D region is disposed above the first S/D region. The semiconductor sheet interconnects the first and second S/D regions and includes a plurality of turns. A method for fabricating the semiconductor device is also disclosed.Type: ApplicationFiled: July 12, 2017Publication date: October 26, 2017Inventors: Hao-Ling Tang, Jon-Hsu Ho, Shao-Hwang Sia, Wen-Hsing Hsieh, Ching-Wei Tsai
-
Patent number: 9754840Abstract: A method of forming a semiconductor device includes forming a fin extending from a substrate. The fin has a source/drain (S/D) region and a channel region. The fin includes a first semiconductor layer and a second semiconductor layer on the first semiconductor layer. The first semiconductor layer has a first composition, and the second semiconductor layer has a second composition different from the first composition. The method further includes removing the first semiconductor layer from the S/D region of the fin such that a first portion of the second semiconductor layer in the S/D region is suspended in a space. The method further includes epitaxially growing a third semiconductor layer in the S/D region, the third semiconductor layer wrapping around the first portion of the second semiconductor layer.Type: GrantFiled: November 16, 2015Date of Patent: September 5, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Hsiung Lin, Chung-Cheng Wu, Carlos H. Diaz, Chih-Hao Wang, Wen-Hsing Hsieh, Yi-Ming Sheu
-
Patent number: 9755075Abstract: Disclosed are methods to form a FinFET diode of high efficiency, designed to resolve the degradation problem with a conventional FinFET diode arising from reduced active area, and a method of fabrication. The FinFET diode has a doped substrate, two spaced-apart groups of semiconductor fin structures, dielectric layers formed between the two groups and among the fin structures for insulation, a plurality of gate structures perpendicularly traversing both groups of the fin structures, and two groups of semiconductor strips respectively formed lengthwise upon the two groups of the fin structures. The two groups of semiconductor strips are doped to have opposite conductivity types, p-type and n-type. In an embodiment, the FinFET diode further has metal contacts formed upon the semiconductor strips. In another embodiment, the semiconductor strips may be integrally formed with the fin structures by epitaxial growth and in-situ doped.Type: GrantFiled: March 21, 2016Date of Patent: September 5, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTDInventors: Hsueh-Shih Fan, Ching-Fang Huang, Chia-Hsin Hu, Min-Chang Liang, Sun-Jay Chang, Shien-Yang Wu, Wen-Hsing Hsieh
-
Patent number: 9711596Abstract: A semiconductor device includes a substrate, a first source/drain (S/D) region, a second S/D region, and a semiconductor sheet. The first S/D region is disposed on the substrate. The second S/D region is disposed above the first S/D region. The semiconductor sheet interconnects the first and second S/D regions and includes a plurality of turns. A method for fabricating the semiconductor device is also disclosed.Type: GrantFiled: December 2, 2014Date of Patent: July 18, 2017Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Hao-Ling Tang, Jon-Hsu Ho, Shao-Hwang Sia, Wen-Hsing Hsieh, Ching-Wei Tsai
-
Patent number: 9698270Abstract: A semiconductor device includes a substrate having a fin structure, the fin structure having a height in a substantially perpendicular direction to the substrate, and having consecutive upper and lower portions along the height, the lower portion being closer to the substrate than the upper portion. The semiconductor device further includes a gate structure wrapping around a portion of the fin structure, the gate structure having a gate dielectric layer disposed around the fin structure, and a gate electrode layer disposed over the gate dielectric layer. The gate electrode layer includes a first gate metal layer formed along both sides of the lower portion of the fin structure, the first gate metal layer having a first workfunction, and a second gate metal layer formed disposed over the first gate metal layer and wrapped around the upper portion of the fin structure, the second gate metal layer having a second workfunction. The first and the second workfunctions are different.Type: GrantFiled: February 26, 2016Date of Patent: July 4, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jean-Pierre Colinge, Wen-Hsing Hsieh
-
Publication number: 20170154973Abstract: A semiconductor device includes a source/drain feature disposed over a substrate. The source/drain feature includes a first nanowire, a second nanowire disposed over the first nanowire, a cladding layer disposed over the first nanowire and the second nanowire and a spacer layer extending from the first nanowire to the second nanowire. The device also includes a conductive feature disposed directly on the source/drain feature such that the conductive feature physically contacts the cladding layer and the spacer layer.Type: ApplicationFiled: November 30, 2015Publication date: June 1, 2017Inventors: Kuo-Cheng Ching, Ching-Fang Huang, Carlos H. Diaz, Chih-Hao Wang, Wen-Hsing Hsieh, Ying-Keung Leung
-
Publication number: 20170141220Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a substrate having a first region and a second region; a first fin feature formed on the substrate within the first region; and a second fin feature formed on the substrate within the second region. The first fin feature includes a first semiconductor feature of a first semiconductor material formed on a dielectric feature that is an oxide of a second semiconductor material. The second fin feature includes a second semiconductor feature of the first semiconductor material formed on a third semiconductor feature of the second semiconductor material.Type: ApplicationFiled: November 16, 2015Publication date: May 18, 2017Inventors: Kuo-Cheng Ching, Ching-Wei Tsai, Chung-Cheng Wu, Chih-Hao Wang, Wen-Hsing Hsieh, Ying-Keung Leung
-
Publication number: 20170140996Abstract: A method of forming a semiconductor device includes forming a fin extending from a substrate. The fin has a source/drain (S/D) region and a channel region. The fin includes a first semiconductor layer and a second semiconductor layer on the first semiconductor layer. The first semiconductor layer has a first composition, and the second semiconductor layer has a second composition different from the first composition. The method further includes removing the first semiconductor layer from the S/D region of the fin such that a first portion of the second semiconductor layer in the S/D region is suspended in a space. The method further includes epitaxially growing a third semiconductor layer in the S/D region, the third semiconductor layer wrapping around the first portion of the second semiconductor layer.Type: ApplicationFiled: November 16, 2015Publication date: May 18, 2017Inventors: Chun-Hsiung Lin, Chung-Cheng Wu, Carlos H. Diaz, Chih-Hao Wang, Wen-Hsing Hsieh, Yi-Ming Sheu
-
Publication number: 20170141112Abstract: A semiconductor includes a first transistor and a second transistor. The first transistor includes a first and a second epitaxial layer, formed of a first semiconductor material. The second epitaxial layer is disposed over the first epitaxial layer. The first transistor also includes a first gate dielectric layer surrounds the first and second epitaxial layers and extends from a top surface of the first epitaxial layer to a bottom surface of the second epitaxial layer and a first metal gate layer surrounding the first gate dielectric layer. The second transistor includes a third epitaxial layer formed of the first semiconductor material and a fourth epitaxial layer disposed directly on the third epitaxial layer and formed of a second semiconductor. The second transistor also includes a second gate dielectric layer disposed over the third and fourth epitaxial layers and a second metal gate layer disposed over the second gate dielectric layer.Type: ApplicationFiled: November 16, 2015Publication date: May 18, 2017Inventors: Kuo-Cheng Ching, Chung-Cheng Wu, Ching-Fang Huang, Wen-Hsing Hsieh, Ying-Keung Leung, Cheng-Ting Chung
-
Patent number: 9620500Abstract: A series-connected transistor structure includes a first source, a first channel-drain structure, a second channel-drain structure, a gate dielectric layer, a gate, a first drain pad and a second drain pad. The first source is over a substrate. The first channel-drain structure is over the first source and includes a first channel and a first drain thereover. The second channel-drain structure is over the first source and substantially parallel to the first channel-drain structure and includes a second channel and a second drain thereover. The gate dielectric layer surrounds the first channel and the second channel. The gate surrounds the gate dielectric layer. The first drain pad is over and in contact with the first drain. The second drain pad is over and in contact with the second drain, in which the first drain pad and the second drain pad are separated from each other.Type: GrantFiled: May 18, 2016Date of Patent: April 11, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chin-Chi Wang, Chien-Chih Lee, Tien-Wei Chiang, Ching-Wei Tsai, Chih-Ching Wang, Jon-Hsu Ho, Wen-Hsing Hsieh
-
Patent number: 9502409Abstract: A multi-gate semiconductor device is formed including a semiconductor substrate. The multi-gate semiconductor device also includes a first transistor including a first fin portion extending above the semiconductor substrate. The first transistor has a first channel region formed therein. The first channel region includes a first channel region portion doped at a first concentration of a first dopant type and a second channel region portion doped at a second concentration of the first dopant type. The second concentration is higher than the first concentration. The first transistor further includes a first gate electrode layer formed over the first channel region. The first gate electrode layer may be of a second dopant type. The first dopant type may be N-type and the second dopant type may be P-type. The second channel region portion may be formed over the first channel region portion.Type: GrantFiled: February 18, 2015Date of Patent: November 22, 2016Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jon-Hsu Ho, Chih-Ching Wang, Ching-Fang Huang, Wen-Hsing Hsieh, Tsung-Hsing Yu, Yi-Ming Sheu, Chih Chieh Yeh, Ken-Ichi Goto, Zhiqiang Wu
-
Publication number: 20160260713Abstract: A series-connected transistor structure includes a first source, a first channel-drain structure, a second channel-drain structure, a gate dielectric layer, a gate, a first drain pad and a second drain pad. The first source is over a substrate. The first channel-drain structure is over the first source and includes a first channel and a first drain thereover. The second channel-drain structure is over the first source and substantially parallel to the first channel-drain structure and includes a second channel and a second drain thereover. The gate dielectric layer surrounds the first channel and the second channel. The gate surrounds the gate dielectric layer. The first drain pad is over and in contact with the first drain. The second drain pad is over and in contact with the second drain, in which the first drain pad and the second drain pad are separated from each other.Type: ApplicationFiled: May 18, 2016Publication date: September 8, 2016Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chin-Chi WANG, Chien-Chih LEE, Tien-Wei CHIANG, Ching-Wei TSAI, Chih-Ching WANG, Jon-Hsu HO, Wen-Hsing HSIEH
-
Publication number: 20160204259Abstract: Disclosed are methods to form a FinFET diode of high efficiency, designed to resolve the degradation problem with a conventional FinFET diode arising from reduced active area, and a method of fabrication. The FinFET diode has a doped substrate, two spaced-apart groups of semiconductor fin structures, dielectric layers formed between the two groups and among the fin structures for insulation, a plurality of gate structures perpendicularly traversing both groups of the fin structures, and two groups of semiconductor strips respectively formed lengthwise upon the two groups of the fin structures. The two groups of semiconductor strips are doped to have opposite conductivity types, p-type and n-type. In an embodiment, the FinFET diode further has metal contacts formed upon the semiconductor strips. In another embodiment, the semiconductor strips may be integrally formed with the fin structures by epitaxial growth and in-situ doped.Type: ApplicationFiled: March 21, 2016Publication date: July 14, 2016Inventors: Hsueh-Shih Fan, Ching-Fang Huang, CHIA-HSIN HU, MIN-CHANG LIANG, SUN-JAY Chang, SHIEN-YANG WU, WEN-HSING HSIEH
-
Publication number: 20160181429Abstract: A semiconductor device includes a substrate having a fin structure, the fin structure having a height in a substantially perpendicular direction to the substrate, and having consecutive upper and lower portions along the height, the lower portion being closer to the substrate than the upper portion. The semiconductor device further includes a gate structure wrapping around a portion of the fin structure, the gate structure having a gate dielectric layer disposed around the fin structure, and a gate electrode layer disposed over the gate dielectric layer. The gate electrode layer includes a first gate metal layer formed along both sides of the lower portion of the fin structure, the first gate metal layer having a first workfunction, and a second gate metal layer formed disposed over the first gate metal layer and wrapped around the upper portion of the fin structure, the second gate metal layer having a second workfunction. The first and the second workfunctions are different.Type: ApplicationFiled: February 26, 2016Publication date: June 23, 2016Inventors: Jean-Pierre Colinge, Wen-Hsing Hsieh
-
Patent number: 9373620Abstract: A series-connected transistor structure includes a first source, a first channel-drain structure, a second channel-drain structure, a gate dielectric layer, a gate, a first drain pad and a second drain pad. The first source is over a substrate. The first channel-drain structure is over the first source and includes a first channel and a first drain thereover. The second channel-drain structure is over the first source and substantially parallel to the first channel-drain structure and includes a second channel and a second drain thereover. The gate dielectric layer surrounds the first channel and the second channel. The gate surrounds the gate dielectric layer. The first drain pad is over and in contact with the first drain. The second drain pad is over and in contact with the second drain, in which the first drain pad and the second drain pad are separated from each other.Type: GrantFiled: September 12, 2014Date of Patent: June 21, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chin-Chi Wang, Chien-Chih Lee, Tien-Wei Chiang, Ching-Wei Tsai, Chih-Ching Wang, Jon-Hsu Ho, Wen-Hsing Hsieh
-
Patent number: 9318322Abstract: System and method for controlling the channel thickness and preventing variations due to formation of small features. An embodiment comprises a fin raised above the substrate and a capping layer is formed over the fin. The channel carriers are repelled from the heavily doped fin and confined within the capping layer. This forms a thin-channel that allows greater electrostatic control of the gate.Type: GrantFiled: November 13, 2014Date of Patent: April 19, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Zhiqiang Wu, Ken-Ichi Goto, Wen-Hsing Hsieh, Jon-Hsu Ho, Chih-Ching Wang, Ching-Fang Huang
-
Patent number: 9293378Abstract: Disclosed are methods to form a FinFET diode of high efficiency, designed to resolve the degradation problem with a conventional FinFET diode arising from reduced active area, and a method of fabrication. The FinFET diode has a doped substrate, two spaced-apart groups of substantially parallel, equally-spaced, elongated semiconductor fin structures, dielectric layers formed between the two groups and among the fin structures for insulation, a plurality of substantially equal-spaced and parallel elongated gate structures perpendicularly traversing both groups of the fin structures, and two groups of semiconductor strips respectively formed lengthwise upon the two groups of the fin structures. The two groups of semiconductor strips are doped to have opposite conductivity types, p-type and n-type. The FinFET diode further has metal contacts formed upon the semiconductor strips. In an embodiment, the semiconductor strips may be integrally formed with the fin structures by epitaxial growth and in-situ doped.Type: GrantFiled: July 6, 2015Date of Patent: March 22, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsueh-Shih Fan, Sun-Jay Chang, Chia-Hsin Hu, Min-Chang Liang, Shien-Yang Wu, Wen-Hsing Hsieh, Ching-Fang Huang
-
Publication number: 20160079239Abstract: A series-connected transistor structure includes a first source, a first channel-drain structure, a second channel-drain structure, a gate dielectric layer, a gate, a first drain pad and a second drain pad. The first source is over a substrate. The first channel-drain structure is over the first source and includes a first channel and a first drain thereover. The second channel-drain structure is over the first source and substantially parallel to the first channel-drain structure and includes a second channel and a second drain thereover. The gate dielectric layer surrounds the first channel and the second channel. The gate surrounds the gate dielectric layer. The first drain pad is over and in contact with the first drain. The second drain pad is over and in contact with the second drain, in which the first drain pad and the second drain pad are separated from each other.Type: ApplicationFiled: September 12, 2014Publication date: March 17, 2016Inventors: Chin-Chi WANG, Chien-Chih LEE, Tien-Wei CHIANG, Ching-Wei TSAI, Chih-Ching WANG, Jon-Hsu HO, Wen-Hsing HSIEH