Abstract: A driving circuit for driving a light source and a projection device are provided. The driving circuit includes a power converter, a detection circuit, and a control circuit. The power converter provides a driving power to the light source. The detection circuit provides a feedback signal according to a current value of the light source. The control circuit receives an operation command and the feedback signal. The control circuit determines whether the driving circuit enters a light-load state according to at least one of the operation command and the feedback signal. When the driving circuit is determined to enter the light-load state, the control circuit controls the power converter to decrease a current value of the driving power and controls the power converter to increase a switching frequency of the driving power. The driving circuit and the projection device may prevent the light source from flickering under the light-load state.

Abstract: A self-powered apparatus is used for various kinds of cycling and indoor exercise devices. The self-powered apparatus includes a pedal unit, a spindle, a generator and an energy storage element. The pedal unit includes an inner surface to form an accommodating space therein. The spindle is accommodated in the accommodating space. The generator includes a stator and a rotor. The stator is disposed on the spindle, the rotor is disposed on the inner surface of the pedal unit, and the rotor surrounds the stator correspondingly and is non-contact with the stator. The energy storage element is electrically coupled to the generator. When the pedal unit is being pedaled to rotate by a rider, the stator is fixed on the spindle, the rotor rotates relatively to the stator and along with the pedal unit, and a power is generated by the generator to charge the energy storage element.

Abstract: A light source module is provided, including: a light board, including a substrate, and a plurality of light-emitting elements arranged at intervals on the substrate; and a separator, located above the substrate, and including a plurality of first ribs, where the plurality of first ribs is cross-connected to form a plurality of interval spaces, to accommodate the light-emitting elements, the first rib forming the interval space has an inner wall, a part of the inner wall in a direction closer to the substrate tapers in a direction far away from the interval space, the inner wall has a first distance farther away from the substrate in a Z-axis direction and has a second distance closer to the substrate, and a projection relationship between the second distance and the first distance onto an XY plane is that the second distance is greater than the first distance.

Abstract: An imaging lens module has an image surface and includes an optical lens assembly, a plurality of monomer structures and a cover member. The optical lens assembly is disposed on an object side of the image surface and defines an optical axis. The optical lens assembly includes a light-blocking element, which includes a light-blocking portion. The light-blocking portion is disposed closer to the optical axis than a portion of the light-blocking element other than the light-blocking portion thereto. The monomer structures are disposed on the object side of the image surface, and each of the monomer structures is extended along a direction parallel to the optical axis. The cover member is disposed on an object side of the optical lens assembly, and the optical axis passes through the cover member. The monomer structures are disposed on the light-blocking portion of the light-blocking element.

Abstract: A semiconductor device is provided, which includes a substrate, a first dielectric layer, a conductive layer, and an insulating capping layer. The first dielectric layer is disposed on the substrate. The conductive layer is disposed on the first dielectric layer. The conductive layer includes a plurality of conductive wires. The insulating capping layer is disposed on the conductive layer, and configured to enclose a plurality of first gaps between the conductive wires to form a plurality of air spacers.

Abstract: A semiconductor device is provided, which includes a substrate, a first dielectric layer, a conductive layer, and an insulating capping layer. The first dielectric layer is disposed on the substrate. The conductive layer is disposed on the first dielectric layer. The conductive layer comprises a plurality of conductive wires. The insulating capping layer is disposed on the conductive layer, and configured to enclose a plurality of first gaps between the conductive wires to form a plurality of air spacers.

Abstract: A vertically integrated micro-bolometer includes an integrated circuit chip, an infrared sensing film, and a metal bonding layer. The integrated circuit chip includes a silicon substrate, a circuit element, and a dielectric layer disposed on the silicon substrate. The infrared sensing film includes a top absorbing layer, a sensing layer, and a bottom absorbing layer. The sensing layer is disposed between the top absorbing layer and the bottom absorbing layer. Materials of the top absorbing layer, the sensing layer, and the bottom absorbing layer are materials compatible with a semiconductor manufacturing process. The metal bonding layer connects the dielectric layer on the silicon substrate in the integrated circuit chip and the bottom absorbing layer of the infrared sensing film to form a vertically integrated micro-bolometer. In one embodiment, the infrared sensing film is divided into a central sensing film, a surrounding sensing film, and a plurality of connecting portions by a plurality of slots.

Abstract: A semiconductor device is provided, including a substrate, a transistor structure, a metal silicide layer, and a metal silicon nitride layer. The transistor structure is formed on the substrate. The transistor structure includes a source region, a drain region and a gate structure. The gate structure is located between the source region and the drain region. The metal silicide layer is formed on the top surface of the source region and the top surface of the drain region, and the metal silicon nitride layer is formed on the surface of the metal silicide layer.

Abstract: Semiconductor devices and methods which utilize a treatment process of a bottom anti-reflective layer are provided. The treatment process may be a physical treatment process in which material is added in order to fill holes and pores within the material of the bottom anti-reflective layer or else the treatment process may be a chemical treatment process in which a chemical reaction is used to form a protective layer. By treating the bottom anti-reflective layer the diffusion of subsequently applied chemicals is reduced or eliminated, thereby helping to prevent defects that arise from such diffusion.

Abstract: A method includes forming a multi-layer stack over a semiconductor substrate, the multi-layer stack comprising a plurality of sacrificial layers that alternate with a plurality of channel layers, forming a dummy gate stack over a top surface and sidewalls of the multi-layer stack, forming first spacers on sidewalls of the dummy gate stack, growing an epitaxial source/drain region that extends through the plurality of sacrificial layers and the plurality of channel layers, forming a metal-semiconductor alloy region on first portions of the epitaxial source/drain region, forming a coating layer on the metal-semiconductor alloy region, wherein during the forming of the metal-semiconductor alloy region and the coating layer, a residual layer is formed on sidewalls of the first spacers, and performing a wet clean process to selectively etch the residual layer from the sidewalls of the first spacers.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a thin film resistor (TFR) layer overlying a semiconductor substrate. A first conductive structure is disposed on an outer region of the TFR layer. The first conductive structure comprises a lateral portion adjacent to a vertical portion. A height of the vertical portion is greater than a height of the lateral portion. A capping structure is disposed on a middle region of the TFR layer and abuts the vertical portion of the first conductive structure.

Abstract: A method of manufacturing a hybrid SOI substrate includes epitaxially growing a sacrificial layer and then an upper semiconductor layer over a semiconductor body. The sacrificial layer may be a heavily doped semiconductor. The heavy doping allows the sacrificial layer to be selectively etched while leaving the upper semiconductor layer largely intact. An SOI region of the semiconductor body is masked while the upper semiconductor layer and the sacrificial layer are etched from a peripheral region of the semiconductor body. A bulk semiconductor is then grown to replace the etched layers on the peripheral region. Holes are formed through the upper semiconductor layer in the SOI region and the sacrificial layer is etched from beneath the upper semiconductor. The holes may then be filled with dielectric leaving a cavity beneath the upper semiconductor layer in the SOI region.

Abstract: A modified polyphenylene ether resin having a structure represented by [Formula 1] is provided.

Abstract: A mouse and a gaming system are respectively provided. The gaming system includes a mouse and an intermediate application program. The mouse includes an operation module, a solid-state disk (SSD), and a processing module. The processing module is connected to an electronic device. When the electronic device runs a game, the processing module records an operation signal generated by an operation of a user in the SSD. The processing module can store settings made by the user to the game and to the mouse in the SSD. When the game is ended in the electronic device, the processing module stores a game result information in the SSD. When the electronic device runs the same game and the same mouse is used to play the same game, the user can read the settings in the SSD to quickly perform the same settings on the game and the mouse.

Abstract: A light blocking sheet having a central axis includes a central hole and a plurality of inner extended portions. The central axis passes through the central hole, which is enclosed by a hole inner surface. The hole inner surface has a first corresponding circle and a second corresponding circle, wherein a diameter of the first corresponding circle is greater than a diameter of the second corresponding circle. The inner extended portions are adjacent to and surround the central hole, wherein each of the inner extended portions is extended and tapered from the first corresponding circle towards the second corresponding circle and includes an inner surface, and the inner surface includes a line pair. The line pair includes two line sections, wherein one end of one line section thereof and one end of the other line section thereof are towards the second corresponding circle and approach to each other.

Abstract: A work piece is positioned on a work piece support, which includes a plurality of temperature control zones. A pre-etch surface topography is determined by measuring a plurality of pre-etch surface heights or thicknesses at a plurality of sites on the work piece. The plurality of sites correspond to the plurality of temperature control zones on the work piece support. At least a first zone of the temperature control zones is heated or cooled based on the measured plurality of pre-etch surface heights or thicknesses, so that the first zone has a first temperature different from a second temperature of a second zone of the temperature control zones. A dry etch is carried out while the first zone has the first temperature different from the second temperature of the second zone of the temperature control zones.

Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) chip comprising a stilted pad structure. A wire underlies a semiconductor substrate on a frontside of the semiconductor substrate. Further, a trench isolation structure extends into the frontside of the semiconductor substrate. The stilted pad structure is inset into a backside of the semiconductor substrate that is opposite the frontside. The stilted pad structure comprises a pad body and a pad protrusion. The pad protrusion underlies the pad body and protrudes from the pad body, through a portion of the semiconductor substrate and the trench isolation structure, towards the wire. The pad body overlies the portion of the semiconductor substrate and is separated from the trench isolation structure by the portion of the semiconductor substrate.

Abstract: A probe cleaning sheet for preventing a probe pin damage and manufacturing method thereof, during the process of a probe pin puncturing the cleaning layer, the material of the cleaning layer and the plurality of high and low density cleaning particles of abrasive material contained in the high density cleaning material and the low density cleaning material are able to efficiently scrape away foreign material from the surface of the probe pin. In addition, the negative charge carried by the silicone itself and its lipophilic characteristics are used to transfer the foreign material on the probe pin to the cleaning layer, and the protective layer is used to prevent overpressure from the probe pin directly impacting the substrate and causing damage to the tips of the probe pin.

Abstract: A network communication apparatus, includes a dispatch device, a first core group with several parallel core units and a second core group with at least one serial core unit. The dispatch device receives several packets contained in several first packet flows, and configured to dispatch several meta data to the parallel core units through several first data flows, and the meta data contain tunnel parameters of the packets. Furthermore, the at least one serial core unit receives the meta data from the parallel core units through several second data flows.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip (IC). The IC comprises a substrate. A resistor overlies the substrate. The resistor comprises a resistive structure overlying the substrate. The resistor also comprises a conductive contact overlying and electrically coupled to the resistive structure. A capping structure is disposed over the conductive contact, wherein the capping structure extends laterally over an upper surface of the conductive contact and vertically along a first sidewall of the conductive contact, such that a lower surface of the capping structure is disposed below a lower surface of the conductive contact.