Abstract: A probe cleaning sheet and a manufacturing method thereof are provided. The manufacturing method includes material preparing step, first printing step, first baking step, first cooling step, second printing step, second baking step, and second cooling step. The probe cleaning sheet includes a silicone glass fiber cloth layer and an abrasive layer set printed on one side of the silicone glass fiber cloth layer. The silicone glass fiber cloth layer includes a plurality of glass fibers and silicone, the silicone is coated on the surface of the glass fibers and in the gap between the glass fibers. The abrasive layer set includes a high-density abrasive layer printed on one side of the silicone glass fiber cloth layer and a low-density abrasive layer printed on the top surface of the high-density abrasive layer and is opposite to the silicone glass fiber cloth layer.

Abstract: A semiconductor device includes a substrate, a fin structure protruding from the substrate, a gate insulating layer covering a channel region formed of the fin structure, a gate electrode layer covering the gate insulating layer, and isolation layers disposed on opposite sides of the fin structure. The fin structure includes a bottom portion, a neck portion, and a top portion sequentially disposed on the substrate. A width of the neck portion is less than a width of the bottom portion and a width of a portion of the top portion.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip (IC). The IC comprises a substrate. A resistor overlies the substrate. The resistor comprises a resistive structure overlying the substrate. The resistor also comprises a conductive contact overlying and electrically coupled to the resistive structure. A capping structure is disposed over the conductive contact, wherein the capping structure extends laterally over an upper surface of the conductive contact and vertically along a first sidewall of the conductive contact, such that a lower surface of the capping structure is disposed below a lower surface of the conductive contact.

Abstract: Embodiments of the present disclosure provide methods of forming a RDL structure with a flat passivation surface. Some embodiments provide a stop layer for chemical mechanical polishing disposed under a passivation layer. Some embodiments provide an extra thickness of passivation deposition and a sacrificial passivation layer for passivation polishing. Some embodiments provide a modified RDL pattern by inserting dummy pattern objects to adjust pattern density.

Abstract: The present application provides a semiconductor structure having dielectric liner and a manufacturing method of the semiconductor structure. The semiconductor structure includes a substrate; a first bit line structure, disposed over the substrate, comprising a first conductive layer, a second conductive layer disposed over the first conductive layer, and a first dielectric layer disposed over the second conductive layer; a second bit line structure, disposed over the substrate, comprising a second dielectric layer, a third conductive layer disposed over the second dielectric layer, and a third dielectric layer disposed over the third conductive layer; a polysilicon layer, disposed over the substrate and surrounded by the first bit line structure and the second bit line structure; a dielectric liner, surrounding at least a portion of the polysilicon layer; and a landing pad, disposed over the polysilicon layer, the dielectric liner and the second bit line structure.

Abstract: A flash memory device includes a substrate, a semiconductor quantum well layer, a semiconductor spacer, a semiconductor channel layer, a gate structure, and source/drain regions. The semiconductor quantum well layer is formed of a first semiconductor material and is disposed over the substrate. The semiconductor spacer is formed of a second semiconductor material and is disposed over the first semiconductor channel layer. The semiconductor channel layer is formed of the first semiconductor material and is disposed over the semiconductor spacer. Thea gate structure is over the second semiconductor channel layer. The source/drain regions are over the substrate and are on opposite sides of the gate structure.

Abstract: The present application provides a semiconductor structure having dielectric liner and a manufacturing method of the semiconductor structure. The semiconductor structure includes a substrate; a first bit line structure, disposed over the substrate, comprising a first conductive layer, a second conductive layer disposed over the first conductive layer, and a first dielectric layer disposed over the second conductive layer; a second bit line structure, disposed over the substrate, comprising a second dielectric layer, a third conductive layer disposed over the second dielectric layer, and a third dielectric layer disposed over the third conductive layer; a polysilicon layer, disposed over the substrate and surrounded by the first bit line structure and the second bit line structure; a dielectric liner, surrounding at least a portion of the polysilicon layer; and a landing pad, disposed over the polysilicon layer, the dielectric liner and the second bit line structure.

Abstract: An amplifier circuit having an adjustable gain is provided. The amplifier circuit includes an input terminal, an output terminal, an amplifier, and an attenuation circuit. The input terminal receives an input signal, which is in turn received by an input terminal of the amplifier. An output terminal of the amplifier outputs the input signal that is amplified. The attenuation circuit is coupled between the output terminal of the amplifier and the output terminal to provide a plurality of attenuation to the input signal that is amplified and generate a first attenuation signal, or between the input terminal and the output terminal to provide the plurality of attenuations to the input signal and generate a second attenuation signal. A difference between an impedance value of the input terminal of the attenuation circuit and an impedance value of the output terminal of the attenuation circuit is within a predetermined range.

Abstract: A device includes a substrate, a first fin, a second fin, a first isolation structure, a second isolation structure, and a gate structure. The first fin extends from a p-type region of the substrate. The second fin extends from an n-type region of the substrate. The first isolation structure is over the p-type region and adjacent to the first fin. The first isolation structure has a bottom surface and opposite first and second sidewalls connected to the bottom surface, a first round corner is between the bottom surface and the first sidewall of the first isolation structure, and the first sidewall is substantially parallel to the second sidewall. The second isolation structure is over the n-type region and adjacent to the first fin. The first isolation structure is deeper than the second isolation structure. The gate structure is over the first isolation structure and covering the first fin.

Abstract: A redistribution structure is provided. A redistribution structure according to the present disclosure includes a first dielectric layer, a mesh metal feature disposed in the first dielectric layer and including a base portion and a frame portion surrounding the base portion, a second dielectric layer disposed over the first dielectric layer and the mesh metal feature, a redistribution feature disposed over the second dielectric layer, a passivation structure disposed over the redistribution feature and the second dielectric layer, a pad opening extending through the passivation structure to expose a top surface of the redistribution feature. The redistribution feature includes a plurality of contact vias that extend through the second dielectric layer to land on the frame portion of the mesh metal feature.

Abstract: An amplifier circuit includes an input terminal used to receive an input signal, an output terminal used to output an output signal, an amplification unit, and a phase adjustment unit. The amplification unit includes an input terminal coupled to the input terminal of the amplifier circuit, an output terminal coupled to the output terminal of the amplifier circuit, a first terminal coupled to a first voltage terminal, and a second terminal coupled to a second voltage terminal. The phase adjustment unit is coupled to the amplification unit. When the amplifier circuit is operated in a first mode, the output signal has a first phase, and when the amplifier circuit is operated in a second mode, the output signal has a second phase. A difference between the first phase and the second phase is within a predetermined range.

Abstract: Disclosed herein is an isolated strain of Roseburia hominis HGM001, which is deposited at Deutsche Sammlung von Mikroorganismen and Zellkulturen GmbH under an accession number DSM 34119. A method for producing butyric acid using the isolated strain of Roseburia hominis HGM001, a fermented culture produced by the method, and a method for alleviating an inflammatory disorder using the fermented culture are also disclosed.

Abstract: Through via structures and methods of fabrication thereof are disclosed herein. An exemplary method includes forming a trench that extends through an insulation layer and into a substrate. The substrate has a first side (e.g., frontside) and a second side (e.g., backside). The insulation layer is disposed over the first side of the substrate. The method includes filling the trench with a dielectric material and performing a thinning process on the second side of the substrate that exposes the dielectric material. After the thinning process and removing the dielectric material from the trench, the method includes forming an electrically conductive structure (e.g., a barrier liner that wraps an electrically conductive plug) in the trench that extends through the substrate from the first side to the second side. A portion of the barrier liner that forms a top of the electrically conductive structure is disposed in the insulation layer.

Abstract: A semiconductor device and method of manufacture are provided. After a patterning of a middle layer, the middle layer is removed. In order to reduce or prevent damage to other underlying layers exposed by the patterning of the middle layer and intervening layers, an inhibitor is included within an etching process in order to inhibit the amount of material removed from the underlying layers.

Abstract: A semiconductor device includes a substrate, a fin structure protruding from the substrate, a gate insulating layer covering a channel region formed of the fin structure, a gate electrode layer covering the gate insulating layer, and isolation layers disposed on opposite sides of the fin structure. The fin structure includes a bottom portion, a neck portion, and a top portion sequentially disposed on the substrate. A width of the neck portion is less than a width of the bottom portion and a width of a portion of the top portion.

Abstract: A semiconductor device includes a patterned substrate, a first barrier layer, a second barrier layer and a conductive layer. The patterned substrate has a trench and a sidewall surrounding the trench. The first barrier layer disposed on a first portion of the sidewall. The second barrier layer with a permittivity from 0.5 to 3.8 is disposed on the first barrier layer and a second portion of the sidewall, in which the second portion of the sidewall is higher than the first portion of the sidewall and neighboring to a top surface of the patterned substrate. A conductive layer fills the trench. A method of manufacturing a semiconductor device is further provided.

Abstract: A flash memory device includes a substrate, a semiconductor quantum well layer, a semiconductor spacer, a semiconductor channel layer, a gate structure, and source/drain regions. The semiconductor quantum well layer is formed of a first semiconductor material and is disposed over the substrate. The semiconductor spacer is formed of a second semiconductor material and is disposed over the first semiconductor channel layer. The semiconductor channel layer is formed of the first semiconductor material and is disposed over the semiconductor spacer. Thea gate structure is over the second semiconductor channel layer. The source/drain regions are over the substrate and are on opposite sides of the gate structure.

Abstract: A work piece is positioned on a work piece support, which includes a plurality of temperature control zones. A pre-etch surface topography is determined by measuring a plurality of pre-etch surface heights or thicknesses at a plurality of sites on the work piece. The plurality of sites correspond to the plurality of temperature control zones on the work piece support. At least a first zone of the temperature control zones is heated or cooled based on the measured plurality of pre-etch surface heights or thicknesses, so that the first zone has a first temperature different from a second temperature of a second zone of the temperature control zones. A dry etch is carried out while the first zone has the first temperature different from the second temperature of the second zone of the temperature control zones.

Abstract: A vertical rhyme machine includes a base, a first actuating mechanism, a top cover and a second actuating mechanism. The first actuating mechanism includes a first motor assembly, a first shaft assembly and two first linkage assemblies. The first motor assembly is disposed at the base. The first shaft assembly includes a first shaft body and two first eccentric linking elements. The two first eccentric linking elements are connected to two ends of the first shaft body, respectively. The second actuating mechanism includes a second motor assembly, a second shaft assembly and two second linkage assemblies. The second motor assembly disposed at the base. The second shaft assembly includes a second shaft body and two second eccentric linking elements. The second shaft body is disposed at the base. The two second eccentric linking elements are connected to two ends of the second shaft body, respectively.

Abstract: An amplifier circuit includes a first amplifier and a second amplifier. The first amplifier receives a first signal and generates a first amplification signal accordingly. The second amplifier receives a second signal and generates a second amplification signal accordingly. The first signal is related to a first frequency band, and the second signal is related to a second frequency band different from the first frequency band. When one of the first amplifier and the second amplifier is in use, the other one of the first amplifier and the second amplifier is unused. The first amplifier and second amplifier are coupled to a reference voltage terminal through a common node. The first amplifier includes a switch coupled between the common node and a stage of the first amplifier, and the switch can be controlled for reducing the loading effect caused by the first amplifier on the second amplifier.