Patents by Inventor Wen Hsu

Wen Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240312840
    Abstract: Through via structures and methods of fabrication thereof are disclosed herein. An exemplary method includes forming a trench that extends through an insulation layer and into a substrate. The substrate has a first side (e.g., frontside) and a second side (e.g., backside). The insulation layer is disposed over the first side of the substrate. The method includes filling the trench with a dielectric material and performing a thinning process on the second side of the substrate that exposes the dielectric material. After the thinning process and removing the dielectric material from the trench, the method includes forming an electrically conductive structure (e.g., a barrier liner that wraps an electrically conductive plug) in the trench that extends through the substrate from the first side to the second side. A portion of the barrier liner that forms a top of the electrically conductive structure is disposed in the insulation layer.
    Type: Application
    Filed: July 10, 2023
    Publication date: September 19, 2024
    Inventors: Lee-Wen Hsu, Liang-Wei Wang, Chih-Pin Chiu, Dian-Hau Chen
  • Publication number: 20240282575
    Abstract: A semiconductor device and method of manufacture are provided. After a patterning of a middle layer, the middle layer is removed. In order to reduce or prevent damage to other underlying layers exposed by the patterning of the middle layer and intervening layers, an inhibitor is included within an etching process in order to inhibit the amount of material removed from the underlying layers.
    Type: Application
    Filed: April 17, 2024
    Publication date: August 22, 2024
    Inventors: Jian-Jou Lian, Yao-Wen Hsu, Neng-Jye Yang, Li-Min Chen, Chia-Wei Wu, Kuan-Lin Chen, Kuo-Bin Huang
  • Patent number: 12068394
    Abstract: A semiconductor device includes a substrate, a fin structure protruding from the substrate, a gate insulating layer covering a channel region formed of the fin structure, a gate electrode layer covering the gate insulating layer, and isolation layers disposed on opposite sides of the fin structure. The fin structure includes a bottom portion, a neck portion, and a top portion sequentially disposed on the substrate. A width of the neck portion is less than a width of the bottom portion and a width of a portion of the top portion.
    Type: Grant
    Filed: May 3, 2021
    Date of Patent: August 20, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Wei Chang, Chiung Wen Hsu, Yu-Ting Weng
  • Publication number: 20240258392
    Abstract: A semiconductor device includes a patterned substrate, a first barrier layer, a second barrier layer and a conductive layer. The patterned substrate has a trench and a sidewall surrounding the trench. The first barrier layer disposed on a first portion of the sidewall. The second barrier layer with a permittivity from 0.5 to 3.8 is disposed on the first barrier layer and a second portion of the sidewall, in which the second portion of the sidewall is higher than the first portion of the sidewall and neighboring to a top surface of the patterned substrate. A conductive layer fills the trench. A method of manufacturing a semiconductor device is further provided.
    Type: Application
    Filed: January 31, 2023
    Publication date: August 1, 2024
    Inventor: Feng Wen HSU
  • Patent number: 12051756
    Abstract: A flash memory device includes a substrate, a semiconductor quantum well layer, a semiconductor spacer, a semiconductor channel layer, a gate structure, and source/drain regions. The semiconductor quantum well layer is formed of a first semiconductor material and is disposed over the substrate. The semiconductor spacer is formed of a second semiconductor material and is disposed over the first semiconductor channel layer. The semiconductor channel layer is formed of the first semiconductor material and is disposed over the semiconductor spacer. Thea gate structure is over the second semiconductor channel layer. The source/drain regions are over the substrate and are on opposite sides of the gate structure.
    Type: Grant
    Filed: January 13, 2022
    Date of Patent: July 30, 2024
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Jiun-Yun Li, Nai-Wen Hsu, Wei-Chih Hou, Yu-Jui Wu, Yen Chuang, Chia-Yu Liu
  • Patent number: 12046477
    Abstract: A work piece is positioned on a work piece support, which includes a plurality of temperature control zones. A pre-etch surface topography is determined by measuring a plurality of pre-etch surface heights or thicknesses at a plurality of sites on the work piece. The plurality of sites correspond to the plurality of temperature control zones on the work piece support. At least a first zone of the temperature control zones is heated or cooled based on the measured plurality of pre-etch surface heights or thicknesses, so that the first zone has a first temperature different from a second temperature of a second zone of the temperature control zones. A dry etch is carried out while the first zone has the first temperature different from the second temperature of the second zone of the temperature control zones.
    Type: Grant
    Filed: January 8, 2021
    Date of Patent: July 23, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming Chyi Liu, Hung-Wen Hsu, Min-Yung Ko
  • Publication number: 20240238144
    Abstract: A vertical rhyme machine includes a base, a first actuating mechanism, a top cover and a second actuating mechanism. The first actuating mechanism includes a first motor assembly, a first shaft assembly and two first linkage assemblies. The first motor assembly is disposed at the base. The first shaft assembly includes a first shaft body and two first eccentric linking elements. The two first eccentric linking elements are connected to two ends of the first shaft body, respectively. The second actuating mechanism includes a second motor assembly, a second shaft assembly and two second linkage assemblies. The second motor assembly disposed at the base. The second shaft assembly includes a second shaft body and two second eccentric linking elements. The second shaft body is disposed at the base. The two second eccentric linking elements are connected to two ends of the second shaft body, respectively.
    Type: Application
    Filed: January 17, 2024
    Publication date: July 18, 2024
    Inventors: Wen-Hsu HSIEH, Po-Chien HSIEH
  • Patent number: 12040757
    Abstract: An amplifier circuit includes a first amplifier and a second amplifier. The first amplifier receives a first signal and generates a first amplification signal accordingly. The second amplifier receives a second signal and generates a second amplification signal accordingly. The first signal is related to a first frequency band, and the second signal is related to a second frequency band different from the first frequency band. When one of the first amplifier and the second amplifier is in use, the other one of the first amplifier and the second amplifier is unused. The first amplifier and second amplifier are coupled to a reference voltage terminal through a common node. The first amplifier includes a switch coupled between the common node and a stage of the first amplifier, and the switch can be controlled for reducing the loading effect caused by the first amplifier on the second amplifier.
    Type: Grant
    Filed: July 19, 2021
    Date of Patent: July 16, 2024
    Assignee: RichWave Technology Corp.
    Inventors: Chih-Sheng Chen, Ching-Wen Hsu, Hsien-Wei Ke
  • Patent number: 12040219
    Abstract: A device includes a substrate, a first fin, a second fin, a first isolation structure, a second isolation structure, and a gate structure. The first fin extends from a p-type region of the substrate. The second fin extends from an n-type region of the substrate. The first isolation structure is over the p-type region and adjacent to the first fin. The first isolation structure has a bottom surface and opposite first and second sidewalls connected to the bottom surface, a first round corner is between the bottom surface and the first sidewall of the first isolation structure, and the first sidewall is substantially parallel to the second sidewall. The second isolation structure is over the n-type region and adjacent to the first fin. The first isolation structure is deeper than the second isolation structure. The gate structure is over the first isolation structure and covering the first fin.
    Type: Grant
    Filed: July 9, 2021
    Date of Patent: July 16, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsien-Chung Huang, Chiung-Wen Hsu, Mei-Ju Kuo, Yu-Ting Weng, Yu-Chi Lin, Ting-Chung Wang, Chao-Cheng Chen
  • Publication number: 20240219239
    Abstract: A vertically integrated micro-bolometer includes an integrated circuit chip, an infrared sensing film, and a metal bonding layer. The integrated circuit chip includes a silicon substrate, a circuit element, and a dielectric layer disposed on the silicon substrate. The infrared sensing film includes a top absorbing layer, a sensing layer, and a bottom absorbing layer. The sensing layer is disposed between the top absorbing layer and the bottom absorbing layer. Materials of the top absorbing layer, the sensing layer, and the bottom absorbing layer are materials compatible with a semiconductor manufacturing process. The metal bonding layer connects the dielectric layer on the silicon substrate in the integrated circuit chip and the bottom absorbing layer of the infrared sensing film to form a vertically integrated micro-bolometer. In one embodiment, the infrared sensing film is divided into a central sensing film, a surrounding sensing film, and a plurality of connecting portions by a plurality of slots.
    Type: Application
    Filed: May 25, 2023
    Publication date: July 4, 2024
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Yu-Wen HSU, Lu-Pu LIAO, Chao-Ta HUANG, Bo-Kai CHAO
  • Publication number: 20240204095
    Abstract: A power device and a method for manufacturing the power device are provided. The power device includes an electrical substrate, an epitaxial layer, a well region, a plurality of doping regions, a plurality of trenches, a first oxidation layer, a second oxidation layer, a polycrystalline silicon filler, two shielding regions, a dielectric layer, and a metallic electrically conductive layer.
    Type: Application
    Filed: March 9, 2023
    Publication date: June 20, 2024
    Inventors: SUNG-NIEN TANG, HO-TAI CHEN, HSIU-WEN HSU
  • Publication number: 20240190139
    Abstract: Provided is a printing system with intelligent color-matching, including a storage device, a printing device, and a processing device. The storage device stores a program, a color-matching dataset, and a color-matching model. The color-matching dataset contains multiple pieces of color-matching data, and each piece of color-matching data includes an ink formula and a corresponding printing color value for the ink formula. The printing device is controlled to produce printed products. The processing device loads the program from the storage device to perform the following tasks: training the color-matching model using the color-matching dataset; inputting the expected color value into the trained color-matching model, and obtaining a predicted formula output by the trained color-matching model; and based on the predicted formula, controlling the printing device to produce the printed product.
    Type: Application
    Filed: December 8, 2023
    Publication date: June 13, 2024
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Hsi-Kang SHIH, Wesley Jen-Yang CHANG, Mei-Wen HSU, Wen-Pin CHUANG, Shinn-Jen CHANG
  • Publication number: 20240194776
    Abstract: A power device and a method for manufacturing the power device are provided. The power device includes an electrical substrate, an epitaxial compound layer, a plurality of gates, a passivation layer, an electrically conductive body, a drain, and a field plate. The electrical substrate has a first surface, an epitaxial drift layer, and a plurality of doping regions. The doping regions are located below the first surface. The epitaxial compound layer is located on the electrical substrate. The gates are located on the epitaxial compound layer. The passivation layer covers the gates and the epitaxial compound layer. The electrically conductive body penetrates the passivation layer and the epitaxial compound layer and extends to the first surface. The drain penetrates the passivation layer and extends to the epitaxial layer. The field plate is located on the passivation layer, shields the gates, and connects to the electrically conductive body.
    Type: Application
    Filed: March 17, 2023
    Publication date: June 13, 2024
    Inventors: SUNG-NIEN TANG, HO-TAI CHEN, HSIU-WEN HSU
  • Patent number: 11996340
    Abstract: A method for making a semiconductor structure includes forming a first fin and a second fin over a substrate. The method includes forming one or more work function layers over the first and second fins. The method includes forming a nitride-based metal film over the one or more work function layers. The method includes covering the first fin with a patternable layer. The method includes removing a second portion of the nitride-based metal film from the second fin, while leaving a first portion of the nitride-based metal film over the first fin substantially intact.
    Type: Grant
    Filed: August 5, 2021
    Date of Patent: May 28, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yao-Wen Hsu, Ying-Liang Chuang
  • Publication number: 20240169615
    Abstract: An electronic device and a non-transitory computer-readable storage medium are provided. The electronic device includes a storage module and a processing module. The storage module is configured to store at least one program instruction. The processing module is coupled to the storage module, and is configured to load the at least one program instruction to perform the following steps: parsing a plurality of cells in an analysis area in a data sheet to identify each of the cells as a formula cell or a non-formula cell; classifying the formula cells so that the formula cells having similar formula expressions fall into the same formula group; analyzing a formula structure of the formula expressions of each formula group to output at least one recommended chart option.
    Type: Application
    Filed: April 3, 2023
    Publication date: May 23, 2024
    Applicant: POTIX CORPORATION
    Inventors: Chih-Heng Chen, Jen-Feng Chao, Wenning Hsu, Ming-Shia Yeh
  • Patent number: 11990339
    Abstract: A semiconductor device and method of manufacture are provided. After a patterning of a middle layer, the middle layer is removed. In order to reduce or prevent damage to other underlying layers exposed by the patterning of the middle layer and intervening layers, an inhibitor is included within an etching process in order to inhibit the amount of material removed from the underlying layers.
    Type: Grant
    Filed: August 2, 2021
    Date of Patent: May 21, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jian-Jou Lian, Yao-Wen Hsu, Neng-Jye Yang, Li-Min Chen, Chia-Wei Wu, Kuan-Lin Chen, Kuo Bin Huang
  • Publication number: 20240153826
    Abstract: Semiconductor devices and methods which utilize a treatment process of a bottom anti-reflective layer are provided. The treatment process may be a physical treatment process in which material is added in order to fill holes and pores within the material of the bottom anti-reflective layer or else the treatment process may be a chemical treatment process in which a chemical reaction is used to form a protective layer. By treating the bottom anti-reflective layer the diffusion of subsequently applied chemicals is reduced or eliminated, thereby helping to prevent defects that arise from such diffusion.
    Type: Application
    Filed: January 11, 2024
    Publication date: May 9, 2024
    Inventors: Yao-Wen Hsu, Ming-Chi Huang, Ying-Liang Chuang
  • Publication number: 20240107148
    Abstract: Camera modules and associated electronic devices and systems are described. A camera module may include a set of housing elements that at least partially defines an interior cavity, a set of lens elements, an image sensor positioned within the interior cavity to receive light through the set of lens elements, and a substrate assembly. The substrate assembly may include a set of rigid substrates, a first set of electrical contacts positioned on a first surface of the set of rigid substrates, and a second set of electrical contacts positioned on a second surface of the set of rigid substrates. The substrate assembly may be positioned such that a first portion of the substrate assembly is positioned inside the interior cavity and a second portion of the substrate assembly extends outside of the interior cavity.
    Type: Application
    Filed: January 26, 2023
    Publication date: March 28, 2024
    Inventors: Angelo M. Alaimo, Wassim Ferose Habeeb Rakuman, Bohan Hao, Ya-Wen Hsu
  • Publication number: 20240088187
    Abstract: Trenches in which to form a back side isolation structure for an array of CMOS image sensors are formed by a cyclic process that allows the trenches to be kept narrow. Each cycle of the process includes etching to add a depth segment to the trenches and coating the depth segment with an etch-resistant coating. The following etch step will break through the etch-resistant coating at the bottom of the trench but the etch-resistant coating will remain in the upper part of the trench to limit lateral etching and substrate damage. The resulting trenches have a series of vertically spaced nodes. The process may result in a 10% increase in photodiode area and a 30-40% increase in full well capacity.
    Type: Application
    Filed: January 3, 2023
    Publication date: March 14, 2024
    Inventors: Chih Cheng Shih, Tsun-Kai Tsao, Jiech-Fun Lu, Hung-Wen Hsu, Bing Cheng You, Wen-Chang Kuo
  • Publication number: 20240069069
    Abstract: A probe pin cleaning pad including a foam layer, a cleaning layer, and a polishing layer is provided. The cleaning layer is disposed between the foam layer and the polishing layer. A cleaning method for a probe pin is also provided.
    Type: Application
    Filed: November 10, 2023
    Publication date: February 29, 2024
    Applicant: Alliance Material Co., Ltd.
    Inventors: Chun-Fa Chen, Yu-Hsuen Lee, Ching-Wen Hsu, Chao-Hsuan Yang, Ting-Wei Lin