Abstract: A device includes a substrate, a first fin, a second fin, a first isolation structure, a second isolation structure, and a gate structure. The first fin extends from a p-type region of the substrate. The second fin extends from an n-type region of the substrate. The first isolation structure is over the p-type region and adjacent to the first fin. The first isolation structure has a bottom surface and opposite first and second sidewalls connected to the bottom surface, a first round corner is between the bottom surface and the first sidewall of the first isolation structure, and the first sidewall is substantially parallel to the second sidewall. The second isolation structure is over the n-type region and adjacent to the first fin. The first isolation structure is deeper than the second isolation structure. The gate structure is over the first isolation structure and covering the first fin.

Abstract: A vertically integrated micro-bolometer includes an integrated circuit chip, an infrared sensing film, and a metal bonding layer. The integrated circuit chip includes a silicon substrate, a circuit element, and a dielectric layer disposed on the silicon substrate. The infrared sensing film includes a top absorbing layer, a sensing layer, and a bottom absorbing layer. The sensing layer is disposed between the top absorbing layer and the bottom absorbing layer. Materials of the top absorbing layer, the sensing layer, and the bottom absorbing layer are materials compatible with a semiconductor manufacturing process. The metal bonding layer connects the dielectric layer on the silicon substrate in the integrated circuit chip and the bottom absorbing layer of the infrared sensing film to form a vertically integrated micro-bolometer. In one embodiment, the infrared sensing film is divided into a central sensing film, a surrounding sensing film, and a plurality of connecting portions by a plurality of slots.

Abstract: A power device and a method for manufacturing the power device are provided. The power device includes an electrical substrate, an epitaxial layer, a well region, a plurality of doping regions, a plurality of trenches, a first oxidation layer, a second oxidation layer, a polycrystalline silicon filler, two shielding regions, a dielectric layer, and a metallic electrically conductive layer.

Abstract: Provided is a printing system with intelligent color-matching, including a storage device, a printing device, and a processing device. The storage device stores a program, a color-matching dataset, and a color-matching model. The color-matching dataset contains multiple pieces of color-matching data, and each piece of color-matching data includes an ink formula and a corresponding printing color value for the ink formula. The printing device is controlled to produce printed products. The processing device loads the program from the storage device to perform the following tasks: training the color-matching model using the color-matching dataset; inputting the expected color value into the trained color-matching model, and obtaining a predicted formula output by the trained color-matching model; and based on the predicted formula, controlling the printing device to produce the printed product.

Abstract: A power device and a method for manufacturing the power device are provided. The power device includes an electrical substrate, an epitaxial compound layer, a plurality of gates, a passivation layer, an electrically conductive body, a drain, and a field plate. The electrical substrate has a first surface, an epitaxial drift layer, and a plurality of doping regions. The doping regions are located below the first surface. The epitaxial compound layer is located on the electrical substrate. The gates are located on the epitaxial compound layer. The passivation layer covers the gates and the epitaxial compound layer. The electrically conductive body penetrates the passivation layer and the epitaxial compound layer and extends to the first surface. The drain penetrates the passivation layer and extends to the epitaxial layer. The field plate is located on the passivation layer, shields the gates, and connects to the electrically conductive body.

Abstract: A method for making a semiconductor structure includes forming a first fin and a second fin over a substrate. The method includes forming one or more work function layers over the first and second fins. The method includes forming a nitride-based metal film over the one or more work function layers. The method includes covering the first fin with a patternable layer. The method includes removing a second portion of the nitride-based metal film from the second fin, while leaving a first portion of the nitride-based metal film over the first fin substantially intact.

Abstract: A semiconductor device and method of manufacture are provided. After a patterning of a middle layer, the middle layer is removed. In order to reduce or prevent damage to other underlying layers exposed by the patterning of the middle layer and intervening layers, an inhibitor is included within an etching process in order to inhibit the amount of material removed from the underlying layers.

Abstract: Semiconductor devices and methods which utilize a treatment process of a bottom anti-reflective layer are provided. The treatment process may be a physical treatment process in which material is added in order to fill holes and pores within the material of the bottom anti-reflective layer or else the treatment process may be a chemical treatment process in which a chemical reaction is used to form a protective layer. By treating the bottom anti-reflective layer the diffusion of subsequently applied chemicals is reduced or eliminated, thereby helping to prevent defects that arise from such diffusion.

Abstract: Camera modules and associated electronic devices and systems are described. A camera module may include a set of housing elements that at least partially defines an interior cavity, a set of lens elements, an image sensor positioned within the interior cavity to receive light through the set of lens elements, and a substrate assembly. The substrate assembly may include a set of rigid substrates, a first set of electrical contacts positioned on a first surface of the set of rigid substrates, and a second set of electrical contacts positioned on a second surface of the set of rigid substrates. The substrate assembly may be positioned such that a first portion of the substrate assembly is positioned inside the interior cavity and a second portion of the substrate assembly extends outside of the interior cavity.

Abstract: Trenches in which to form a back side isolation structure for an array of CMOS image sensors are formed by a cyclic process that allows the trenches to be kept narrow. Each cycle of the process includes etching to add a depth segment to the trenches and coating the depth segment with an etch-resistant coating. The following etch step will break through the etch-resistant coating at the bottom of the trench but the etch-resistant coating will remain in the upper part of the trench to limit lateral etching and substrate damage. The resulting trenches have a series of vertically spaced nodes. The process may result in a 10% increase in photodiode area and a 30-40% increase in full well capacity.

Abstract: A probe pin cleaning pad including a foam layer, a cleaning layer, and a polishing layer is provided. The cleaning layer is disposed between the foam layer and the polishing layer. A cleaning method for a probe pin is also provided.

Abstract: A backside illumination (BSI) image sensor and a method of forming the same are provided. A device includes a substrate and a plurality of photosensitive regions in the substrate. The substrate has a first side and a second side opposite to the first side. The device further includes an interconnect structure on the first side of the substrate, and a plurality of recesses on the second side of the substrate. The plurality of recesses extend into a semiconductor material of the substrate.

Abstract: A fan control system is provided, which is used for dissipating heat from a computer device. The fan control system includes a control interface and multiple fan modules. Each one of the fan modules includes a controller, a fan, and a sensor. The controller correspondingly controls a rotational speed of the fan according to environment data transmitted by the connected sensor. The controller transmits real-time fan information to the control interface, and the real-time fan information includes the environment data, identification data, wind direction data, and rotational speed data. The control interface receives the real-time fan information transmitted by the fan modules, and the control interface controls at least one of the fans to change a current rotational speed according to operation information and the real-time fan information transmitted by the fan modules. The fan control system allows the computer device to achieve a good heat-dissipation effect.

Abstract: A semiconductor device and a method of fabricating a semiconductor device are provided herein. The semiconductor device includes a substrate; a fin structure arranged on the substrate and including a ridge portion and a bottom portion between the ridge portion and the substrate, wherein the ridge portion comprises a channel region and a fin region between the channel region and the bottom portion, a critical dimension of the bottom portion in a cross-fin direction is gradually increased toward the substrate to twice or more of a critical dimension of the channel region in the cross-fin direction; a metal gate structure disposed on the fin structure extending the cross-fin direction; and an epitaxy region disposed beside the metal gate structure in a lengthwise direction of the fin structure and connected to the fin structure.

Abstract: Semiconductor devices and methods which utilize a treatment process of a bottom anti-reflective layer are provided. The treatment process may be a physical treatment process in which material is added in order to fill holes and pores within the material of the bottom anti-reflective layer or else the treatment process may be a chemical treatment process in which a chemical reaction is used to form a protective layer. By treating the bottom anti-reflective layer the diffusion of subsequently applied chemicals is reduced or eliminated, thereby helping to prevent defects that arise from such diffusion.

Abstract: An imaging lens assembly includes a lens element and a light blocking element. The lens element is configured to define an optical axis, and the optical axis passes through the lens element. The light blocking element includes a light through hole and a plurality of light diminishing structures. The optical axis passes through the light through hole, the light through hole is formed by connecting a plurality of sidelines to define a polygonal contour. The light diminishing structures are regularly disposed along the polygonal contour, wherein the light diminishing structures are configured to undulate at least one portion of each of the sidelines, so that the at least one portion of each of the sidelines is a non-straight line.

Abstract: A work piece is positioned on a work piece support, which includes a plurality of temperature control zones. A pre-etch surface topography is determined by measuring a plurality of pre-etch surface heights or thicknesses at a plurality of sites on the work piece. The plurality of sites correspond to the plurality of temperature control zones on the work piece support. At least a first zone of the temperature control zones is heated or cooled based on the measured plurality of pre-etch surface heights or thicknesses, so that the first zone has a first temperature different from a second temperature of a second zone of the temperature control zones. A dry etch is carried out while the first zone has the first temperature different from the second temperature of the second zone of the temperature control zones.

Abstract: A probe pin cleaning pad including a release layer or composite plate, an adhesive layer, a substrate layer, a cleaning layer, and a polishing layer is provided. The adhesive layer is disposed on the release layer or composite plate. The substrate layer is disposed on the adhesive layer. The cleaning layer is disposed on the substrate layer. The polishing layer is disposed on the cleaning layer. A cleaning method for a probe pin is also provided.

Abstract: A manufacturing method of electronic components includes the steps of: providing an insulating layer including a first region and a second region; providing a first metal layer disposed in the first region of the insulating layer; providing a second metal layer disposed on the first metal layer; providing a metal line in the second region of the insulating layer, wherein the metal line is electrically connected to the first metal layer; and removing the metal line to form an electronic component, wherein the electronic component includes the insulating layer; and a first metal bump disposed on the insulating layer and including: the first metal layer disposed on the insulating layer; and the second metal layer disposed on the first metal layer.

Abstract: A mouse and a gaming system are respectively provided. The gaming system includes a mouse and an intermediate application program. The mouse includes an operation module, a solid-state disk (SSD), and a processing module. The processing module is connected to an electronic device. When the electronic device runs a game, the processing module records an operation signal generated by an operation of a user in the SSD. The processing module can store settings made by the user to the game and to the mouse in the SSD. When the game is ended in the electronic device, the processing module stores a game result information in the SSD. When the electronic device runs the same game and the same mouse is used to play the same game, the user can read the settings in the SSD to quickly perform the same settings on the game and the mouse.