Patents by Inventor Wen Hsu

Wen Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8188700
    Abstract: An apparatus and a method for driving a sensorless motor are described and shown in the specification and drawings, where the method includes steps as follows. First, a control signal is acquired, where the control signal has information of a predetermined rotational speed. Next, energy is supplied and progressively increased to the sensorless motor, so as to rotate a rotor of the sensorless motor. Then, a position of the rotor is detected. Finally, the energy is gradually regulated so that the sensorless motor is maintained at the predetermined rotational speed.
    Type: Grant
    Filed: September 16, 2009
    Date of Patent: May 29, 2012
    Assignee: inergy Technology Inc.
    Inventors: Chien-Chung Tseng, Hsien-Wen Hsu, Chien-Jen Hsieh
  • Publication number: 20120112766
    Abstract: An electromagnetic induction coordinate detecting method for detecting the trace of at least one electromagnetic pointing device on an electromagnetic sensor board is disclosed. The method includes the following steps: first, a delayed period for each electromagnetic pointing device is pre-determined. Then, whether a board-trigger signal from the electromagnetic sensor board is received is determined. If yes, the electromagnetic pointing device emits an electromagnetic signal after the delayed period. Finally, the electromagnetic sensor board calculates the coordinate and the pressure of each electromagnetic pointing device according to the received electromagnetic signal.
    Type: Application
    Filed: June 17, 2011
    Publication date: May 10, 2012
    Applicant: WALTOP INTERNATIONAL CORPORATION
    Inventors: CHUNG-WEN HSU, CHENG-LU LIU
  • Publication number: 20120099009
    Abstract: This invention provides an optical lens assembly comprising, in order from an object side to an image side: a first lens element with positive refractive power; a second lens element with positive refractive power; a third lens element with negative refractive power having a concave object-side surface and a convex image-side surface, at least one of the object-side and image-side surfaces thereof being aspheric; and a fourth lens element with positive refractive power having an aspheric object-side surface and an aspheric image-side surface; wherein the number of lens elements with refractive power is four.
    Type: Application
    Filed: February 23, 2011
    Publication date: April 26, 2012
    Applicant: LARGAN PRECISION CO., LTD.
    Inventors: Chih Wen Hsu, Hsin Hsuan Huang
  • Patent number: 8164620
    Abstract: A stereo projection optical system includes an image engine configured for providing light superimposed spatial information, a color selector positioned to receive a light output of the image engine, a transmission-type light modulator positioned to receive an emergent light of the color selector. The color selector is configured for selectively modifying the polarization of the light output according to the wavelength of the light output. The transmission-type light modulator alternates between a dark state and a bright state. From the foregoing, it will be apparent that the stereo projection optical system according to the present invention provides advantages in that its structure can be simplified with the reduction of its size by synthesizing lift and right image signals by displaying the stereoscopic image signal using a single projector.
    Type: Grant
    Filed: December 7, 2007
    Date of Patent: April 24, 2012
    Assignee: Hon Hai Precision Idnustry Co., Ltd.
    Inventors: Chien-Wen Hsu, Chia-Hung Kao, Huan-Liang Lo, Sheng-Chung Huang
  • Patent number: 8153490
    Abstract: A fabrication method of a power semiconductor structure with reduced gate impedance is provided. Firstly, a polysilicon gate is formed in a substrate. Then, dopants are implanted into the substrate with the substrate being partially shielded by the polysilicon gate. Afterward, an isolation layer is formed to cover the polysilicon gate. Thereafter, a thermal drive-in process is carried out to form at least a body surrounding the polysilicon gate. Then, the isolation layer is removed to expose the polysilicon gate. Afterward, a metal layer is deposited on the dielectric layer and the polysilicon gate, and a self-aligned silicide layer is formed on the polysilicon gate by using a thermal process.
    Type: Grant
    Filed: August 20, 2010
    Date of Patent: April 10, 2012
    Assignee: Great Power Semiconductor Corp.
    Inventor: Hsiu Wen Hsu
  • Patent number: 8130524
    Abstract: A bi-directional DC to DC power converter includes two DC sources, two inductors respectively connected to the two DC sources, a first switch and a second switch respectively connected to the two inductors, two capacitors respectively connected to the two switches, and a third switch connected between the two inductors. The first, second and third switches are respectively connected reversely with a diode in parallel. When the third switch is alternately turned on and off and the first and second switches are always turned off, the power converter operates as a boost power converter and electric energy flows from the two DC sources to the two capacitors. When the third switch is always turned off and the first and second switches are synchronously turned on or off, the power converter operates as a buck power converter and electric energy flows from the two capacitors to the two DC sources.
    Type: Grant
    Filed: July 8, 2009
    Date of Patent: March 6, 2012
    Assignee: Ablerex Electronics Co., Ltd.
    Inventors: Yi-Hu Lee, Wen Hsu, Chin-Chang Wu, Hung-Liang Chou, Ya-Tsung Feng
  • Publication number: 20120049338
    Abstract: In one embodiment, a semiconductor device package includes: (1) a substrate unit; (2) connecting elements disposed adjacent to a periphery of the substrate unit and extending upwardly from an upper surface of the substrate unit; (3) a semiconductor device disposed adjacent to the upper surface of the substrate unit and electrically connected to the substrate unit; and (4) a package body disposed adjacent to the upper surface of the substrate unit and covering the semiconductor device. A lateral surface of the package body is substantially aligned with a lateral surface of the substrate unit. The package body defines openings that at least partially expose respective ones of the connecting elements. At least one of the connecting elements has a width WC, and at least one of the openings has a width WU adjacent to an upper surface of the package body, such that WU>WC.
    Type: Application
    Filed: November 7, 2011
    Publication date: March 1, 2012
    Inventors: Kuang-Hsiung Chen, Chi-Chih Shen, Jen-Chuan Chen, Wen-Hsiung Chang, Hui-Shan Chang, Pei-Yu Hsu, Fa-Hao Wu, Chen-Yu Chia, Chi-Chih Chu, Cheng-Yi Weng, Ya-Wen Hsu
  • Publication number: 20120044211
    Abstract: An optical touch locating system and method thereof is disclosed herein. The method includes the following steps. A step is used for activating the coordinate detecting module. A step is used for calculating the distance between two optical touch apparatuses. A step is used for sequentially locating a plurality of anchor points. When indicating to detect a first anchor point, a step is used to touch one of four corners on a display device by a touch object. A step is used for sequentially detecting and locating the remaining anchor points. At final step, according to the distance between two optical touch apparatuses and the coordinates of the anchor points, the touch working area. is confirmed.
    Type: Application
    Filed: March 7, 2011
    Publication date: February 23, 2012
    Applicant: WALTOP INTERNATIONAL CORPORATION
    Inventors: CHUNG-WEN HSU, CHUNG-FUU MAO, WEI-CHOU CHEN
  • Publication number: 20120045877
    Abstract: A fabrication method of a power semiconductor structure with reduced gate impedance is provided. Firstly, a polysilicon gate is formed in a substrate. Then, dopants are implanted into the substrate with the substrate being partially shielded by the polysilicon gate. Afterward, an isolation layer is formed to cover the polysilicon gate. Thereafter, a thermal drive-in process is carried out to form at least a body surrounding the polysilicon gate. Then, the isolation layer is removed to expose the polysilicon gate. Afterward, a metal layer is deposited on the dielectric layer and the polysilicon gate, and a self-aligned silicide layer is formed on the polysilicon gate by using a thermal process.
    Type: Application
    Filed: August 20, 2010
    Publication date: February 23, 2012
    Inventor: Hsiu Wen Hsu
  • Patent number: 8114762
    Abstract: A method for manufacturing trench MOSFET device with low gate charge includes the steps of providing a substrate of first conductivity type; forming an epitaxial layer of first conductivity type on the substrate; forming a body region of second conductivity type in the epitaxial layer, the body region extends downwards from the surface of the epitaxial layer; forming a plurality of trenches in the epitaxial layer, the body region having the trenches formed therethrough; forming a first insulating layer on the body region and on an inner surface of each trench; forming a ploy-silicon spacer on the first insulating layer on an inner side-wall of each trench; filling a dielectric structure in the lower portion of each trench; and filling a ploy-silicon structure on top of the dielectric structure in each trench. Through the trench MOSFET device, the gate capacitance and resistance thereof are reduced so the performance is increased.
    Type: Grant
    Filed: May 6, 2009
    Date of Patent: February 14, 2012
    Assignee: Niko Semiconductor Co., Ltd.
    Inventors: Hsiu-Wen Hsu, Chun Wei Ni, Kao-Way Tu
  • Publication number: 20120029391
    Abstract: A Bilateral Upper Limbs Motor Recovery Rehabilitation and Evaluation System for Patients with Stroke which gets feedback from the feeling of body about sense of sight or auditory sense, etc to let inspector's pair of hands process forward, back, drawing and multiple actions, and let strokes can execute task training of kinematic parameter diversification about multiple strength, spped, acceleration, etc to process rehabilitation that relate to the action-status of body and estimate the status of restoration. Devices of file at least includes a pair of double-axle connecting rod structure for upper limbs, an unit for physiological signal collection, an unit for processing estimated of rehabilitation and an unit of multimedia display.
    Type: Application
    Filed: September 24, 2010
    Publication date: February 2, 2012
    Inventors: Wen-Hsu Sung, Shun-Hua Wei, Chueh-Ho Lin, Wen-Wei Tsai, Yu-Da Chen
  • Patent number: 8104354
    Abstract: A capacitive sensor includes a substrate, at least one first electrode, at least one second electrode, a sensing device, at least one anchor base, at least one movable frame, and a plurality of spring members. The first and second electrodes are disposed on the substrate, and the anchor base surrounds the first and second electrodes and is disposed on the substrate. The movable frame surrounds the sensing device. Some of the spring members connect the movable frame and the sensing device, and the other spring members connect the movable frame and the anchor base. The sensing device and the first electrode are both sensing electrodes. The movable frame is disposed above the second electrode, and cooperates with the second electrode to act as a capacitive driver.
    Type: Grant
    Filed: September 8, 2010
    Date of Patent: January 31, 2012
    Assignee: Industrial Technology Research Institute
    Inventors: Yu Wen Hsu, Chao Ta Huang, Jing Yuan Lin, Sheah Chen
  • Publication number: 20120013243
    Abstract: The present invention provides a phosphor composition for AC LEDs, which is represented by the following formula (I): M1?x?ySi2O2?wN2+2w/3:Eux,Ry??(I) wherein, M, R, x, y, and w are defined the same as the specification. In addition, the present invention also provides an AC LED manufactured with the same.
    Type: Application
    Filed: September 8, 2010
    Publication date: January 19, 2012
    Applicant: Forward Electronics Co., Ltd
    Inventors: Ru-Shi Liu, Chiao-Wen Yeh, Hui-Wen Hsu, Wen-Hsiung Li, Jung-Chien Chang, Yu-Bing Lan
  • Publication number: 20120001276
    Abstract: One embodiment discloses an apparatus integrating a microelectromechanical system device with a circuit chip which comprises a circuit chip, a microelectromechanical system device, a sealing ring, and a lid. The circuit chip comprises a substrate and a plurality of metal bonding areas. The substrate has an active surface with electrical circuit area, and the metal bonding areas are disposed on the active surface and electrically connected to the electrical circuits. The microelectromechanical system device comprises a plurality of bases and at least one sensing element. The bases are connected to at least one of the metal bonding areas. The at least one sensing element is elastically connected to the bases. The sealing ring surrounds the bases, and is connected to at least one of the metal bonding areas. The lid is opposite to the active surface of the circuit chip, and is connected to the sealing ring to have a hermetic chamber which seals the sensing element and the active surface of the circuit chip.
    Type: Application
    Filed: June 30, 2011
    Publication date: January 5, 2012
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chao Ta HUANG, Shih Ting Lin, Yu Wen Hsu
  • Publication number: 20110316077
    Abstract: A power semiconductor structure with schottky diode is provided. In the step of forming the gate structure, a separated first polysilicon structure is also formed on the silicon substrate. Then, the silicon substrate is implanted with dopants by using the first polysilicon structure as a mask to form a body and a source region. Afterward, a dielectric layer is deposited on the silicon substrate and an open penetrating the dielectric layer and the first polysilicon structure is formed so as to expose the source region and the drain region below the body. The depth of the open is smaller than the greatest depth of the body. Then, a metal layer is filled into the open to electrically connect to the source region and the drain region.
    Type: Application
    Filed: June 23, 2010
    Publication date: December 29, 2011
    Applicant: GREAT POWER SEMICONDUCTOR CORP.
    Inventors: HSIU WEN HSU, CHUN YING YEH
  • Publication number: 20110318895
    Abstract: A fabrication method of a trenched power MOSFET is provided. A pattern layer having a first opening is formed on a substrate. A portion of the substrate is removed, using the pattern layer as a mask, to form a trench in the substrate. A width of the trench is expanded. A gate oxide layer is formed on a surface of the trench. A portion of the gate oxide layer on a bottom of the trench is removed, using the pattern layer as a mask, to form a second opening in the gate oxide layer. The width of the expanded trench is greater than that of the second opening. A thick oxide layer is formed in the second opening. Heavily doped regions are formed beside the thick oxide layer. A gate is formed in the trench. A body layer surrounding the trench is formed. Sources are formed beside the trench.
    Type: Application
    Filed: September 6, 2011
    Publication date: December 29, 2011
    Applicant: NIKO SEMICONDUCTOR CO., LTD.
    Inventors: Kou-Way Tu, Hsiu-Wen Hsu, Yi-Yun Tsai, Yuan-Shun Chang
  • Patent number: 8082368
    Abstract: A display device for indicating connection statuses of a communication channel between two systems is disclosed, the communication channel having a plurality of communication links. The display device comprises a detecting circuit coupled to the communication channel for detecting a plurality of link statuses of the communication links; an indicator controller coupled to the detecting circuit for determining the connection statuses of the communication channel according to the link statuses; and an LED indicator coupled to the indicator controller for displaying in a plurality of statuses according to the connection statuses from the indicator controller; wherein the connection statuses comprise a first connection status indicating that all the link statuses are “ON”, a second connection status indicating that all the link statuses are “OFF”, and a third connection status indicating that at least one of the link statuses is “ON” and at least one of the link statuses is “OFF”.
    Type: Grant
    Filed: April 21, 2006
    Date of Patent: December 20, 2011
    Assignee: Infortrend Technology, Inc.
    Inventors: Mien-Wen Hsu, Chen-Cheng Lin, Ying-Wen Lin
  • Patent number: 8080457
    Abstract: A fabrication method of a trenched power semiconductor structure with low gate charge is provided. Firstly, a substrate is provided. Then, a gate trench is formed in the substrate. Afterward, a dielectric layer is formed on the inner surfaces of the gate trench. Then, a spacer is formed on the dielectric layer covering the sidewall of the gate trench. Thereafter, a plug structure is formed in the space at the bottom of the gate trench, which is defined by the spacer. Then, a portion of the spacer is removed with the dielectric structure and the plug structure as an etching mask. Thereafter, a portion of the dielectric layer is removed with the remained spacer as an etching mask to expose the inner surface of the upper portion of the gate trench. Afterward, with the remained spacer being kept, a gate dielectric layer is formed on the inner surface of the upper portion of the gate trench, and then a polysilicon gate is filled into the upper portion of the gate trench.
    Type: Grant
    Filed: November 2, 2010
    Date of Patent: December 20, 2011
    Assignee: Great Power Semiconductor Corp.
    Inventor: Hsiu-Wen Hsu
  • Patent number: 8080824
    Abstract: A semiconductor material structure includes at least one region capable of generating electrons and holes each having an associated mean kinetic energy during operation. A material layer in proximity to the region provides an associated potential energy larger than the mean kinetic energy associated with the generated electrons and the mean kinetic energy associated with the holes.
    Type: Grant
    Filed: November 15, 2006
    Date of Patent: December 20, 2011
    Assignee: Academia Sinica
    Inventors: Kuei-Hsien Chen, Chien-Hung Lin, Chia-Wen Hsu, Li-Chyong Chen
  • Patent number: D653468
    Type: Grant
    Filed: September 10, 2010
    Date of Patent: February 7, 2012
    Assignee: Kuang Yu Metal Working Co., Ltd.
    Inventor: Wen-Hsu Hsieh