Abstract: A semiconductor electronic device structure includes an active area array disposed in a substrate, an isolation structure, a plurality of recessed gate structures, a plurality of word lines, and a plurality of bit lines. The active area array a plurality of active area columns and a plurality of active area rows, defining an array of active areas. The substrate has two recesses formed at the central region thereof. Each recessed gate structure is respectively disposed in the recess. A protruding structure is formed on the substrate in each recess. A STI structure of the isolation structure is arranged between each pair of adjacent active area rows. Word lines are disposed in the substrate, each electrically connecting the gate structures there-under. Bit lines are disposed above the active areas, forming a crossing pattern with the word lines.

Abstract: A hydroforming method for metal produces hardware having a throat in only one side and having approximately right-angled corners without causing thinning and breakage. The method includes using a working fluid to exert a liquid pressure on a metal embryo and cooperating with a push rod of a hydroforming mold to supply material from the lower edge, forcing the side sheet metals to bulge. Furthermore, by using the hydroforming mold to provide a downwardly pressing active force on the metal embryo, under feeding of the downwardly pressing active force cooperating with continuous liquid pressure, the metal embryo deforms and bulges such that each corner of the metal embryo and the wall corners of the die cavity of the hydroforming mold have approximately the same angles. Hardware, every angle of which approximates a right angle, can be obtained after removing the hydroforming mold. This method can also be used to obtain a metal box.

Abstract: A semiconductor structure includes a substrate having thereon at least one conductive region; a plurality of cylinder-shaped electrodes disposed on the substrate, wherein each of the cylinder-shaped electrodes has a horizontal portion that is in direct contact with the at least one conductive region and a vertical sidewall portion connecting the horizontal portion; an upper support structure comprising a first lattice structure that is situated in a first horizontal level that is lower than a tip portion of each of the cylinder-shaped electrodes; and a lower support structure comprising a second lattice structure that interlocks middle portions of the cylinder-shaped electrodes.

Abstract: Embodiments of the present invention provide a mode switching method and apparatus, which relate to the communications field and are used to improve user experience. The method includes: when a user equipment UE is in a state of accessing a first network in a first network mode of a first communications mode, determining, by the UE, whether the first network supports a first subsystem; enabling, by the UE, if the UE determines that the first network does not support the first subsystem and when the UE does not access a second network in the first communications mode, a second communications mode and accessing the second network in the second communications mode; and sending, by the UE, a first registration request message to the second network. The embodiments of the present invention are applicable to a service transmission scenario.

Abstract: An inductor structure includes a substrate, a protection layer, a patterned first conductive layer, copper bumps, a passivation layer, a diffusion barrier layer, and an oxidation barrier layer. The protection layer is located on the substrate. The bond pads of the substrate are respectively exposed through protection layer openings. The first conductive layer is located on the surfaces of the bond pads and the protection layer adjacent to the protection layer openings. The copper bumps are located on the first conductive layer. The passivation layer is located on the protection layer and the copper bumps. At least one of the copper bumps is exposed through a passivation layer opening. The diffusion barrier layer is located on the copper bump that is exposed through the passivation layer opening. The oxidation barrier layer is located on the diffusion barrier layer.

Abstract: A semiconductor having through-silicon via includes a substrate, an outer dielectric liner, an inner dielectric liner and a conductive contacting layer. The substrate has a top surface and a bottom surface and defining at least one through-silicon via going through the top surface toward the bottom surface. The outer dielectric liner covers the top surface of the substrate. The inner dielectric liner covers a wall of the through-silicon via. The thickness of the inner dielectric liner reduces from the top surface toward the bottom surface. The conductive contacting liner over fills the through-silicon via and is exposed on the top surface.

Abstract: A circuit board assembly comprises a first circuit board and a second circuit board. A connector socket is mounted on the first circuit board, and a connector plug is mounted on the second circuit board. A handle assembly is attached to either the first circuit board or the second circuit board. The handle assembly comprises a base member attached to either the first circuit board or the second circuit board and first and second rotating members pivotably attached to opposite ends of the base member. When the first rotating member and the second rotating member are rotated away from the base member, the connector plug is disengaged from the connector socket. When the first rotating member and the second rotating member are rotated towards the base member, the connector plug is inserted into the connector socket.

Abstract: A manufacturing method of an inductor structure includes the following steps. A protection layer is formed on a substrate, such that bond pads of the substrate are respectively exposed form protection layer openings of the protection layer. A conductive layer is formed on the bond pads and the protection layer. A patterned first photoresist layer is formed on the conductive layer. Copper bumps are respectively formed on the conductive layer located in the first photoresist layer openings. A patterned second photoresist layer is formed on the first photoresist layer, such that at least one of the copper bumps is exposed through second photoresist layer opening and the corresponding first photoresist layer opening. A diffusion barrier layer and an oxidation barrier layer are formed on the copper bump. The first and second photoresist layers, and the conductive layer not covered by the copper bumps are removed.

Abstract: A fan frame includes a blade holder, a pair of ventilation plates, and at least one side plate. The pair of ventilation plates is attached to opposite sides of the blade holder along a first direction and includes a pair of securing blocks. The at least one side plate is attached to the blade holder along a second direction substantially perpendicular to the first direction and located between the pair of ventilation plates. The pair of mounting slots is defined in the at least one side plate and engaged with the pair of securing blocks, thereby securing the pair of ventilation plates and the at least one side plate to the blade holder.

Abstract: An e-fuse device disclosed herein includes an anode and a cathode that are conductively coupled to the doped region formed in a substrate, wherein the anode includes a first metal silicide region positioned on the doped region and a first conductive metal-containing contact that is positioned above and coupled to the first metal silicide region, and the cathode includes a second metal silicide region positioned on the doped region and a second conductive metal-containing contact that is positioned above and conductively coupled to the second metal silicide region. A method disclosed herein includes forming a doped region in a substrate for an e-fuse device and performing at least one common process operation to form a first conductive structure on the doped region of the e-fuse device and a second conductive structure on a source/drain region of a transistor.

Abstract: A mounting apparatus for securing a data storage device includes a mounting tray, which includes a bottom wall, two sidewalls perpendicularly extending from the bottom wall, a positioning protrusion extending from the bottom wall, and a latching protrusion extending from each sidewall. The latching protrusions are configured for being received in latching holes defined in the data storage device. Each sidewall is elastically deformable. A distance between the two sidewalls is substantially equal to a width of the data storage device. An extending direction of the positioning protrusion is substantially perpendicular to an extending direction of the latching protrusion. An electronic device with the mounting apparatus is further disclosed.

Abstract: A fan assembly used in an electronic device is disclosed. The fan assembly includes a fan and the casing securing the fan. The casing includes a top plate, a front plate, a rear plate and two side plates. The top plate comprises a plurality of mounting pieces and a mounting portion located on each mounting piece. The front plate is secured to the fan. The rear plate is secured to the fan and opposite to the front plate. The two side plates are secured to the front plate and the rear plate. Each side plate comprises two positioning pieces, and each positioning piece defines a positioning hole. The plurality of mounting pieces abuts the two positioning pieces of the two side plates, and the mounting piece is engaged in the positioning hole.

Abstract: A mounting apparatus includes a tray receiving a storage device and a retaining device. The retaining device includes a base member, an arm member, a pressing member, and a sliding member. The base member is secured to the tray. The arm member is attached to the base member and includes a hook. The pressing member is moveably attached to the base member. The sliding member is slidably attached to the base member and abuts the pressing member. The sliding member includes an engaging edge engaged with the hook. The pressing member is moveable in a first direction that is substantially perpendicular to the base member, to move the sliding member in a second direction that is substantially parallel to the base member, so that the engaging edge is disengaged from the hook.

Abstract: A lifting apparatus for a printed circuit board includes a first handle and a second handle. The first handle is secured adjacent a first edge of the printed circuit board. The first handle includes a main body and a pair of mounting pieces. The pair of mounting pieces is secured on the printed circuit board. The main body is slidably mounted on the pair of mounting pieces. The second handle is secured adjacent a second edge of the printed circuit board which is opposite to the first edge.

Abstract: A method for fabricating a semiconductor memory includes the following steps. Active areas are defined in a substrate. An oxide layer is then formed on the active areas. The oxide layer is subjected to a surface treatment. A first polysilicon layer, a buffer layer and a hard mask are deposited. Recessed access devices are formed in an array region of the substrate. After the recessed access devices are formed, the hard mask and the buffer layer are removed to thereby form transistors in a peripheral region. A second polysilicon layer is deposited on the first polysilicon layer. The first and second polysilicon layers are then etched into a gate structure.

Abstract: A memory unit includes a substrate, at least one charge storage element, at least one first recessed access element, and an isolation portion. The substrate has a surface and the first recessed access element is disposed in an active area of the substrate and extending from the surface into the substrate. The first recessed access element is electrically connected to the charge storage element and induces in the substrate a first depletion region. The isolation portion is adjacent to the active area and extending from the surface into the substrate. The isolation portion includes a trenched isolating barrier and a second recessed access element. The second recessed access element is disposed in the trenched isolating barrier and induces in the substrate a second depletion region merging with the first depletion region.

Abstract: A semiconductor electronic device structure includes an active area array disposed in a substrate, an isolation structure, a plurality of recessed gate structures, a plurality of word lines, and a plurality of bit lines. The active area array a plurality of active area columns and a plurality of active area rows, defining an array of active areas. The substrate has two recesses formed at the central region thereof. Each recessed gate structure is respectively disposed in the recess. A protruding structure is formed on the substrate in each recess. A STI structure of the isolation structure is arranged between each pair of adjacent active area rows. Word lines are disposed in the substrate, each electrically connecting the gate structures there-under. Bit lines are disposed above the active areas, forming a crossing pattern with the word lines.

Abstract: A semiconductor structure having buried word line formed in a trench in a semiconductor substrate includes a gate oxide layer, a gate conductor, a gate cap layer, a blocking layer, and an isolation structure. The gate oxide layer is formed on the inner surface of the trench, the gate conductor is formed in the trench, and the gate cap layer is formed on the gate conductor. The blocking layer surrounds a bottom portion of the gate conductor, and the bottom portion of the gate conductor is isolated from the gate oxide layer by the blocking layer. The isolation structure surrounds a top portion of the gate conductor and in contact with the top end of the blocking layer. The top portion of the gate conductor is isolated from the gate oxide layer and the from the gate cap layer by the isolation structure.

Abstract: A mounting apparatus for bezel includes a first mounting structure secured, and a chassis. A plurality of first hooks is defined in the bezel. The chassis includes a first sidewall. The first sidewall defines an installation groove. The first mounting structure includes an installation member, and a locking member slidably installed in the installation member. The installation member is engaged with the plurality of first hooks. The locking member is slidably installed on the installation member. The installation member defines a through hole, and a latching portion is located on the locking member. The latching portion extends through the through hole to be engaged in the installation groove and the latching portion can be disengaged from the installation groove when the locking member slides.

Abstract: A blocking mechanism includes a chassis, a blocking member, and a resilient member. The chassis is configured to secure a circuit board, the chassis comprising a locking structure. The blocking member is configured to abut the circuit board, for preventing the circuit board from sliding towards the blocking member. The blocking member includes a positioning structure slidably engaged with the locking structure. The resilient member is secured to the blocking member and engaged with the locking structure for preventing the blocking member from sliding relative to the locking structure. The resilient member is resiliently deformable. When the resilient member is disengaged from the locking structure, the blocking member is slidable relative to the chassis to disengage the locking structure from the positioning structure.