Patents by Inventor Wen Hu

Wen Hu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • LAMP CONTROL SYSTEM AND CONTROL SYSTEM
    Publication number: 20160323979
    Abstract: A lamp control system includes at least one first lamp network, at least one second lamp network and a lamp control gateway. The first lamp network is configured to emit light and to transmit a first message, and includes a first physical layer. The second lamp network is configured to emit light and to transmit a first message, and includes a second physical layer different from the first physical layer. The lamp control gateway includes a processing module that is configured to receive the first message and the second message and to convert the first message and the second message in such a way that a first converted message and a second converted message comply with a predefined protocol.
    Type: Application
    Filed: April 28, 2016
    Publication date: November 3, 2016
    Inventors: Wei-Wen HU, Peng-Hsiang WU, Jon-Hong LIN, Chun-Yi SUN
  • METHOD FOR SWITCHING STANDBY MODE, USER EQUIPMENT UE, AND NETWORK DEVICE
    Publication number: 20160227447
    Abstract: The present invention discloses a method, including: when user equipment camps on a first network, sending, by the UE to a network device, a single-domain registration request needed when the network device performs mobility management on the UE. The single-domain registration request carries a first IE, and the first IE identifies that the UE has a CS domain voice capability. The UE is a single card dual standby terminal, the UE is currently in a standby state in both the first network and a second network, the first network supports a PS domain service, and the second network supports a CS domain service. If the UE receives a second IE fed back according to the single-domain registration request by the network device, exiting, by the UE, the standby state in the second network, where the second IE identifies that the first network supports CSFB.
    Type: Application
    Filed: April 14, 2016
    Publication date: August 4, 2016
    Inventor: Wen Hu
  • Despin device
    Patent number: 9382019
    Abstract: A despin device includes a central base installed in an outer rotational ring. The outer rotational ring includes a plurality of through-holes extending from an inner wall face thereof through an outer wall face thereof. Masses are symmetrically installed in ball grooves of the central base and the through-holes of the outer rotational ring. The masses are connected by a connecting line extending through a line cutter and tensioned by a tensioning device. Cables are wrapped around an outer periphery of the central base. Each cable includes an end attached to one of the masses. A plurality of release-hitch devices is provided. Each release-hitch device includes a hitch member fixed to the central base and a disengagement member releasably engaged with the hitch member and fixed to the other end of one of the cables.
    Type: Grant
    Filed: October 1, 2014
    Date of Patent: July 5, 2016
    Assignee: National Pingtung University of Science & Technology
    Inventors: Hui-Wen Hu, Ming-Tzu Ho, Pin-Tsung Wu, Huan-Sheng Chen
  • TRANSISTOR STRUCTURE AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20160104782
    Abstract: A method of manufacturing a transistor structure includes a step of implanting a light dosage into a substrate at a bit line junction and two cell side junctions, and a step of implanting a light dosage into the bit line junction an additional time. A uniform region having a substantially uniform dopant concentration is formed at the bit line junction. The dopant concentration of the uniform region is higher than that of the cell side junctions and higher than that of the region of the bit line junction under the uniform region.
    Type: Application
    Filed: October 8, 2014
    Publication date: April 14, 2016
    Inventors: TZUNG-HAN LEE, NENG-TAI SHIH, YAW-WEN HU
  • THIN FILM AND METHOD FOR MANUFACTURING THIN FILM
    Publication number: 20160056068
    Abstract: The present invention provides a kind of thin film and a fabrication method of thin films. The method comprises implanting ions under the surface of the original substrate by ion-implanting method, hence creating a thin film layer, a splitting layer and a remaining material layer on the original substrate; wherein, the thin film layer is on the surface of the original substrate and the splitting layer is between the thin film layer and the remaining material layer; the implanted ions are distributed in the splitting layer. Make the target substrate be in contact with the thin film layer of the original substrate, and then bond the original substrate to the target substrate by wafer-bonding method to form a bonding unit. Place the bonding unit into a prepared container to heat the bonding unit, so that the thin film layer is split off from the remaining material layer.
    Type: Application
    Filed: August 27, 2013
    Publication date: February 25, 2016
    Applicant: Jinan Jingzheng Electronics Co., Ltd.
    Inventors: Hui Hu, Wen Hu
  • Method for forming self-aligned isolation trenches in semiconductor substrate and semiconductor device
    Patent number: 9230967
    Abstract: The instant disclosure relates to a method for forming self-aligned isolation trenches in semiconductor substrate, comprising the following steps. The first step is providing a semiconductor substrate defined a plurality of active areas thereon. The next step is forming at least two buried bit lines in each of the active areas and an insulating structure disposed above and opposite to the at least two buried bit lines. The next step is forming a self-aligned spacer on the sidewalls of each of the insulating structures. The last step is selectively removing the semiconductor substrate with the self-aligned spacers as masks to form a plurality of isolation trenches.
    Type: Grant
    Filed: April 14, 2014
    Date of Patent: January 5, 2016
    Assignee: Inotera Memories, Inc.
    Inventors: Tzung-Han Lee, Yaw-Wen Hu
  • SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
    Publication number: 20150348871
    Abstract: A semiconductor device includes a substrate having a first side and a second side opposite to the first side; a through substrate via (TSV) structure protruding from a surface of the substrate on the second side; a block layer conformally covering the surface of the substrate and the TSV structure; a first dielectric layer covering the block layer except for a portion of the block layer that is directly on the TSV structure; a second dielectric layer on the first dielectric layer; and a damascened circuit pattern in the second dielectric layer. The second dielectric layer is in direct contact with the first dielectric layer. The damascened circuit pattern is in direct contact with the TSV structure.
    Type: Application
    Filed: May 29, 2014
    Publication date: December 3, 2015
    Applicant: INOTERA MEMORIES, INC.
    Inventors: Hsu Chiang, Yaw-Wen Hu, Neng-Tai Shih, Tzung-Han Lee
  • SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREFOR
    Publication number: 20150349072
    Abstract: A semiconductor electronic device structure includes a substrate having a trench disposed therein, a gate electrode disposed in the trench, and a gate dielectric layer disposed on the surface in the trench. The substrate and the gate electrode are electrically insulated from each other by the gate dielectric layer. The substrate further has a pair of doped areas. The doped areas each are vertically disposed along the two respective lateral sides of the trench. The doped areas each have a first portion and a second portion arranged atop the first portion. The first portion extends vertically to the portion of the substrate that is aligned to the gate electrode. The lateral dimension of the first portion is smaller than the lateral dimension of the second portion, and the doping concentration of the first portion is lighter than the doping concentration of the second portion.
    Type: Application
    Filed: May 29, 2014
    Publication date: December 3, 2015
    Applicant: INOTERA MEMORIES, INC.
    Inventors: TZUNG-HAN LEE, YAW-WEN HU, NENG-TAI SHIH, HENG HAO HSU, YU JING CHANG, HSU CHIANG
  • E-FUSE STRUCTURE FOR AN INTEGRATED CIRCUIT PRODUCT
    Publication number: 20150340319
    Abstract: An e-fuse device disclosed herein includes an anode and a cathode that are conductively coupled to the doped region formed in a substrate, wherein the anode includes a first metal silicide region positioned on the doped region and a first conductive metal-containing contact that is positioned above and coupled to the first metal silicide region, and the cathode includes a second metal silicide region positioned on the doped region and a second conductive metal-containing contact that is positioned above and conductively coupled to the second metal silicide region. A method disclosed herein includes forming a doped region in a substrate for an e-fuse device and performing at least one common process operation to form a first conductive structure on the doped region of the e-fuse device and a second conductive structure on a source/drain region of a transistor.
    Type: Application
    Filed: August 4, 2015
    Publication date: November 26, 2015
    Inventors: Xiaoqiang Zhang, O Sung Kwon, Jianghu Yan, Wen-Hu Hung, Roderick Miller, HongLiang Shen
  • Manufacturing method of capacitor structure and semiconductor device using the same
    Patent number: 9184166
    Abstract: The instant disclosure relates to a semiconductor device which includes a semiconductor substrate, at least one patterned reinforcing layer, a plurality of lower electrodes, and a supporting layer. The at least one patterned reinforcing layer is arranged above the semiconductor substrate, wherein the at least one patterned reinforcing layer has a plurality of reinforcing structures configured to define a plurality of alignment apertures. The lower electrodes are arranged on the semiconductor substrate, wherein N of the lower electrodes pass through each of the alignment apertures, where N is an integer greater than or equal to 1. The supporting layer is arranged above the at least one patterned reinforcing layer and between the lower electrodes.
    Type: Grant
    Filed: May 8, 2014
    Date of Patent: November 10, 2015
    Assignee: Inotera Memories, Inc.
    Inventors: Tzung-Han Lee, Yaw-Wen Hu, Vishnu Kumar Agarwal
  • Semiconductor structure
    Patent number: 9171847
    Abstract: A semiconductor structure includes a semiconductor substrate, an active area in the semiconductor substrate, two trenches intersecting the active area to thereby divide the active area into a source region and two drain regions spaced apart from the source region, a saddle-shaped N+/N?/N+ structure in the source region of the active area; and two N+ drain doping regions in the two drain regions, respectively.
    Type: Grant
    Filed: October 2, 2014
    Date of Patent: October 27, 2015
    Assignee: INOTERA MEMORIES, INC.
    Inventors: Tzung-Han Lee, Neng-Tai Shih, Yaw-Wen Hu
  • SEMICONDUCTOR DEVICE
    Publication number: 20150294972
    Abstract: The instant disclosure relates to a semiconductor device includes a semiconductor substrate, a plurality of buried bit lines, a plurality of insulating structures, and a plurality of self-aligned spacers. The semiconductor substrate has a plurality of active areas defined thereon. The buried bit lines are disposed in the semiconductor substrate, wherein two of the buried bit lines are positioned in each of the active areas. The insulating structures are disposed on the semiconductor substrate, wherein each of the insulating structures is positioned on and opposite to the two of the buried bit lines. The self-aligned spacers are disposed on the sidewalls of the insulating structures respectively to partially expose the surface of the semiconductor substrate.
    Type: Application
    Filed: June 8, 2015
    Publication date: October 15, 2015
    Inventors: TZUNG-HAN LEE, YAW-WEN HU
  • Methods of forming an e-fuse for an integrated circuit product and the resulting e-fuse structure
    Patent number: 9159667
    Abstract: An e-fuse device disclosed herein includes an anode and a cathode that are conductively coupled to the doped region formed in a substrate, wherein the anode includes a first metal silicide region positioned on the doped region and a first conductive metal-containing contact that is positioned above and coupled to the first metal silicide region, and the cathode includes a second metal silicide region positioned on the doped region and a second conductive metal-containing contact that is positioned above and conductively coupled to the second metal silicide region. A method disclosed herein includes forming a doped region in a substrate for an e-fuse device and performing at least one common process operation to form a first conductive structure on the doped region of the e-fuse device and a second conductive structure on a source/drain region of a transistor.
    Type: Grant
    Filed: July 26, 2013
    Date of Patent: October 13, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Xiaoqiang Zhang, O Sung Kwon, Jianghu Yan, Wen-Hu Hung, Roderick Miller, HongLiang Shen
  • SEMICONDUCTOR DEVICE CAPABLE OF SUPPRESSING WARPING
    Publication number: 20150243597
    Abstract: A semiconductor device includes a substrate having a front side and a rear side, a plurality of dielectric layers on the front side, a plurality of interconnection circuit structures in the dielectric layers, and at least one backside passivation layer on the rear side. The backside passivation layer and the top passivation layer are made of the same material and have substantially the same thickness.
    Type: Application
    Filed: February 25, 2014
    Publication date: August 27, 2015
    Applicant: INOTERA MEMORIES, INC.
    Inventors: Hsu Chiang, Yaw-Wen Hu
  • PASSIVE COMPONENT STRUCTURE AND MANUFACTURING METHOD THEREOF
    Publication number: 20150214162
    Abstract: A manufacturing method of a passive component structure includes the following steps. A protection layer is formed on a substrate, and bond pads of the substrate are respectively exposed through protection layer openings. A conductive layer is formed on the bond pads and the protection layer. A patterned photoresist layer is formed on the conductive layer, and the conductive layer adjacent to the protection layer openings is exposed through photoresist layer openings. Copper bumps are respectively electroplated on the conductive layer. The photoresist layer and the conductive layer not covered by the copper bumps are removed. A passivation layer is formed on the copper bumps and the protection layer, and at least one of the copper bumps is exposed through a passivation layer opening. A diffusion barrier layer and an oxidation barrier layer are chemically plated in sequence on the copper bump.
    Type: Application
    Filed: January 23, 2015
    Publication date: July 30, 2015
    Inventors: Jiun-Yen LAI, Yu-Wen HU, Bai-Yao LOU, Chia-Sheng LIN, Yen-Shih HO, Hsin KUAN
  • MANUFACTURING METHOD OF CAPACITOR STRUCTURE AND SEMICONDUCTOR DEVICE USING THE SAME
    Publication number: 20150206883
    Abstract: The instant disclosure relates to a semiconductor device which includes a semiconductor substrate, at least one patterned reinforcing layer, a plurality of lower electrodes, and a supporting layer. The at least one patterned reinforcing layer is arranged above the semiconductor substrate, wherein the at least one patterned reinforcing layer has a plurality of reinforcing structures configured to define a plurality of alignment apertures. The lower electrodes are arranged on the semiconductor substrate, wherein N of the lower electrodes pass through each of the alignment apertures, where N is an integer greater than or equal to 1. The supporting layer is arranged above the at least one patterned reinforcing layer and between the lower electrodes.
    Type: Application
    Filed: May 8, 2014
    Publication date: July 23, 2015
    Applicant: INOTERA MEMORIES, INC.
    Inventors: TZUNG-HAN LEE, YAW-WEN HU, VISHNU KUMAR AGARWAL
  • Memory unit, memory unit array and method of manufacturing the same
    Patent number: 9070740
    Abstract: A memory unit includes a substrate, at least one charge storage element, at least one first recessed access element, and an isolation portion. The substrate has a surface and the first recessed access element is disposed in an active area of the substrate and extending from the surface into the substrate. The first recessed access element is electrically connected to the charge storage element and induces in the substrate a first depletion region. The isolation portion is adjacent to the active area and extending from the surface into the substrate. The isolation portion includes a trenched isolating barrier and a second recessed access element. The second recessed access element is disposed in the trenched isolating barrier and induces in the substrate a second depletion region merging with the first depletion region.
    Type: Grant
    Filed: June 19, 2013
    Date of Patent: June 30, 2015
    Assignee: Inotera Memories, Inc.
    Inventors: Tzung-Han Lee, Yaw-Wen Hu, Chung-Yuan Lee, Hsu Chiang, Sheng-Hsiung Wu, Hung Chang Liao
  • Semiconductor structure
    Patent number: 9070782
    Abstract: A semiconductor structure includes multiple buried gates which are disposed in a substrate and have a first source and a second source, an interlayer dielectric layer covering the multiple buried gates and the substrate as well as a core dual damascene plug including a first plug, a second plug and an insulating slot. The insulating slot is disposed between the first plug and the second plug so that the first plug and the second plug are mutually electrically insulated. The first plug and the second plug respectively penetrate the interlayer dielectric layer and are respectively electrically connected to the first source and the second source.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: June 30, 2015
    Assignee: INOTERA MEMORIES, INC.
    Inventors: Tzung-Han Lee, Yaw-Wen Hu, Hung-Chang Liao, Chung-Yuan Lee, Hsu Chiang, Sheng-Hsiung Wu
  • METHOD FOR FORMING SELF-ALIGNED ISOLATION TRENCHES IN SEMICONDUCTOR SUBSTRATE AND SEMICONDUCTOR DEVICE
    Publication number: 20150171162
    Abstract: The instant disclosure relates to a method for forming self-aligned isolation trenches in semiconductor substrate, comprising the following steps. The first step is providing a semiconductor substrate defined a plurality of active areas thereon. The next step is forming at least two buried bit lines in each of the active areas and an insulating structure disposed above and opposite to the at least two buried bit lines. The next step is forming a self-aligned spacer on the sidewalls of each of the insulating structures. The last step is selectively removing the semiconductor substrate with the self-aligned spacers as masks to form a plurality of isolation trenches.
    Type: Application
    Filed: April 14, 2014
    Publication date: June 18, 2015
    Applicant: Inotera Memories, Inc.
    Inventors: TZUNG-HAN LEE, YAW-WEN HU
  • INK COMPOSITION AND CIRCUIT BOARD AND METHOD FOR PRODUCING THE SAME
    Publication number: 20150156871
    Abstract: An ink composition and a circuit board and a method for producing the same are provided. The ink composition comprises: an acrylic resin; an epoxy resin; a polyester resin; a curing agent; and an active powder comprising a modified metal compound, in which the metal element of the modified metal compound is at least one selected from the group consisting of Zn, Cr, Co, Cu, Mn, Mo, and Ni.
    Type: Application
    Filed: January 27, 2015
    Publication date: June 4, 2015
    Inventors: Haibin LI, Wen HU, Hongye LIN