Abstract: A manufacturing method of an inductor structure includes the following steps. A protection layer is formed on a substrate, such that bond pads of the substrate are respectively exposed form protection layer openings of the protection layer. A conductive layer is formed on the bond pads and the protection layer. A patterned first photoresist layer is formed on the conductive layer. Copper bumps are respectively formed on the conductive layer located in the first photoresist layer openings. A patterned second photoresist layer is formed on the first photoresist layer, such that at least one of the copper bumps is exposed through second photoresist layer opening and the corresponding first photoresist layer opening. A diffusion barrier layer and an oxidation barrier layer are formed on the copper bump. The first and second photoresist layers, and the conductive layer not covered by the copper bumps are removed.

Abstract: A connector structure (100) for a flexible light strip (10) includes a cable joint (110) and an insulation body (200). The cable joint (110) includes a housing (120) and a plurality of conductive terminals (130) assembled in the housing (120). Each of the conductive terminals (130) includes a piercing portion (150). The insulation body (200) has a first end (210) and a second end (220) communicating with the first end (210). The flexible light strip (10) is inserted into the first end (210), and the housing (120) is inserted into the second end (220). The piercing portion (150) is parallel to the flexible light strip (10) and correspondingly pierces the flexible light trip (10) to be electrically coupled to the same. Therefore, the connector structure (100) achieves fast assembly and improves efficiency and reliability for connection.

Abstract: A mounting device for a display module includes a positioning member and an installation member. The positioning member includes a limiting portion and a positioning piece. The limiting portion defines a first receiving slot. The positioning piece defines a cutout. The installation member is secured to the positioning member and includes an elastically deformable limiting block. The installation member defines a second receiving slot and a limiting slot. A limiting rib is located on the limiting block and in the limiting slot. The first receiving slot and the second receiving slot rotatably receive a rotating shaft of the display module therebetween. The limiting block abuts a connecting shaft connected to the rotating shaft and blocks the connecting shaft in the limiting slot. The cutout is adapted to receive the connecting shaft when the rotating shaft is rotated to rotate the connecting shaft out of the limiting slot.

Abstract: A method of demodulating a signal packet includes steps of: determining whether a pulse width of each of pulses of one of bits of the signal packet is associated with bit 0 or bit 1; updating first counting data associated with a number of the pulses that define bit 0, and determining whether the first counting data is greater than a first threshold value; deciding that said one of the bits of the signal packet is a bit 0; updating second counting data associated with a number of the pulses that define bit 1, and determining whether the second counting data is greater than the second threshold value; deciding that said one of the bits of the signal packet is a bit 1.

Abstract: A recoverable device for memory product includes a substrate, a plurality of device dies and at least one local interconnect layer. The device dies are embedded inside the substrate. The at least one local interconnect layer is disposed on an upper surface of the substrate, and configured to route the device dies to a plurality of electrical terminals on an uppermost surface of the local interconnect layer relative to the substrate.

Abstract: A connector assembly (100) with a bidirectional clamping structure is used for assembling a light emitting component (10). The connector assembly (100) includes a first pivot member (110) and a second pivot member (200). The first pivot member (110) includes a body (120), a cover (150), a first pivot portion (170) connected to one side of the body (120) and the cover (150), and a wire groove (180) at the other side. The second pivot member (200) is detachably pivotally connected to the first pivot member (110). The second pivot member (200) includes a base (210). The base (210) includes a second pivot portion (220) asymmetrically disposed with respect to the first pivot portion (170) and an insertion slot (260). The insertion slot (260) is provided for insertion of the light emitting component (10) and is disposed corresponding to the other side of the second pivot portion (220).

Abstract: An ink composition and a circuit board and a method for producing the same are provided. The ink composition comprises: an acrylic resin; an epoxy resin; a polyester resin; a curing agent; and an active powder comprising a modified metal compound, in which the metal element of the modified metal compound is at least one selected from the group consisting of Zn, Cr, Co, Cu, Mn, Mo, and Ni.

Abstract: A semiconductor electronic device structure includes a substrate having a trench disposed therein, a gate electrode disposed in the trench, and a gate dielectric layer disposed on the surface in the trench. The substrate and the gate electrode are electrically insulated from each other by the gate dielectric layer. The substrate further has a pair of doped areas. The doped areas each are vertically disposed along the two respective lateral sides of the trench. The doped areas each have a first portion and a second portion arranged atop the first portion. The first portion extends vertically to the portion of the substrate that is aligned to the gate electrode. The lateral dimension of the first portion is smaller than the lateral dimension of the second portion, and the doping concentration of the first portion is lighter than the doping concentration of the second portion.

Abstract: A lamp control system includes at least one first lamp network, at least one second lamp network and a lamp control gateway. The first lamp network is configured to emit light and to transmit a first message, and includes a first physical layer. The second lamp network is configured to emit light and to transmit a first message, and includes a second physical layer different from the first physical layer. The lamp control gateway includes a processing module that is configured to receive the first message and the second message and to convert the first message and the second message in such a way that a first converted message and a second converted message comply with a predefined protocol.

Abstract: The present invention discloses a method, including: when user equipment camps on a first network, sending, by the UE to a network device, a single-domain registration request needed when the network device performs mobility management on the UE. The single-domain registration request carries a first IE, and the first IE identifies that the UE has a CS domain voice capability. The UE is a single card dual standby terminal, the UE is currently in a standby state in both the first network and a second network, the first network supports a PS domain service, and the second network supports a CS domain service. If the UE receives a second IE fed back according to the single-domain registration request by the network device, exiting, by the UE, the standby state in the second network, where the second IE identifies that the first network supports CSFB.

Abstract: A despin device includes a central base installed in an outer rotational ring. The outer rotational ring includes a plurality of through-holes extending from an inner wall face thereof through an outer wall face thereof. Masses are symmetrically installed in ball grooves of the central base and the through-holes of the outer rotational ring. The masses are connected by a connecting line extending through a line cutter and tensioned by a tensioning device. Cables are wrapped around an outer periphery of the central base. Each cable includes an end attached to one of the masses. A plurality of release-hitch devices is provided. Each release-hitch device includes a hitch member fixed to the central base and a disengagement member releasably engaged with the hitch member and fixed to the other end of one of the cables.

Abstract: A method of manufacturing a transistor structure includes a step of implanting a light dosage into a substrate at a bit line junction and two cell side junctions, and a step of implanting a light dosage into the bit line junction an additional time. A uniform region having a substantially uniform dopant concentration is formed at the bit line junction. The dopant concentration of the uniform region is higher than that of the cell side junctions and higher than that of the region of the bit line junction under the uniform region.

Abstract: The present invention provides a kind of thin film and a fabrication method of thin films. The method comprises implanting ions under the surface of the original substrate by ion-implanting method, hence creating a thin film layer, a splitting layer and a remaining material layer on the original substrate; wherein, the thin film layer is on the surface of the original substrate and the splitting layer is between the thin film layer and the remaining material layer; the implanted ions are distributed in the splitting layer. Make the target substrate be in contact with the thin film layer of the original substrate, and then bond the original substrate to the target substrate by wafer-bonding method to form a bonding unit. Place the bonding unit into a prepared container to heat the bonding unit, so that the thin film layer is split off from the remaining material layer.

Abstract: The instant disclosure relates to a method for forming self-aligned isolation trenches in semiconductor substrate, comprising the following steps. The first step is providing a semiconductor substrate defined a plurality of active areas thereon. The next step is forming at least two buried bit lines in each of the active areas and an insulating structure disposed above and opposite to the at least two buried bit lines. The next step is forming a self-aligned spacer on the sidewalls of each of the insulating structures. The last step is selectively removing the semiconductor substrate with the self-aligned spacers as masks to form a plurality of isolation trenches.

Abstract: A semiconductor electronic device structure includes a substrate having a trench disposed therein, a gate electrode disposed in the trench, and a gate dielectric layer disposed on the surface in the trench. The substrate and the gate electrode are electrically insulated from each other by the gate dielectric layer. The substrate further has a pair of doped areas. The doped areas each are vertically disposed along the two respective lateral sides of the trench. The doped areas each have a first portion and a second portion arranged atop the first portion. The first portion extends vertically to the portion of the substrate that is aligned to the gate electrode. The lateral dimension of the first portion is smaller than the lateral dimension of the second portion, and the doping concentration of the first portion is lighter than the doping concentration of the second portion.

Abstract: A semiconductor device includes a substrate having a first side and a second side opposite to the first side; a through substrate via (TSV) structure protruding from a surface of the substrate on the second side; a block layer conformally covering the surface of the substrate and the TSV structure; a first dielectric layer covering the block layer except for a portion of the block layer that is directly on the TSV structure; a second dielectric layer on the first dielectric layer; and a damascened circuit pattern in the second dielectric layer. The second dielectric layer is in direct contact with the first dielectric layer. The damascened circuit pattern is in direct contact with the TSV structure.

Abstract: An e-fuse device disclosed herein includes an anode and a cathode that are conductively coupled to the doped region formed in a substrate, wherein the anode includes a first metal silicide region positioned on the doped region and a first conductive metal-containing contact that is positioned above and coupled to the first metal silicide region, and the cathode includes a second metal silicide region positioned on the doped region and a second conductive metal-containing contact that is positioned above and conductively coupled to the second metal silicide region. A method disclosed herein includes forming a doped region in a substrate for an e-fuse device and performing at least one common process operation to form a first conductive structure on the doped region of the e-fuse device and a second conductive structure on a source/drain region of a transistor.

Abstract: The instant disclosure relates to a semiconductor device which includes a semiconductor substrate, at least one patterned reinforcing layer, a plurality of lower electrodes, and a supporting layer. The at least one patterned reinforcing layer is arranged above the semiconductor substrate, wherein the at least one patterned reinforcing layer has a plurality of reinforcing structures configured to define a plurality of alignment apertures. The lower electrodes are arranged on the semiconductor substrate, wherein N of the lower electrodes pass through each of the alignment apertures, where N is an integer greater than or equal to 1. The supporting layer is arranged above the at least one patterned reinforcing layer and between the lower electrodes.

Abstract: A semiconductor structure includes a semiconductor substrate, an active area in the semiconductor substrate, two trenches intersecting the active area to thereby divide the active area into a source region and two drain regions spaced apart from the source region, a saddle-shaped N+/N?/N+ structure in the source region of the active area; and two N+ drain doping regions in the two drain regions, respectively.

Abstract: The instant disclosure relates to a semiconductor device includes a semiconductor substrate, a plurality of buried bit lines, a plurality of insulating structures, and a plurality of self-aligned spacers. The semiconductor substrate has a plurality of active areas defined thereon. The buried bit lines are disposed in the semiconductor substrate, wherein two of the buried bit lines are positioned in each of the active areas. The insulating structures are disposed on the semiconductor substrate, wherein each of the insulating structures is positioned on and opposite to the two of the buried bit lines. The self-aligned spacers are disposed on the sidewalls of the insulating structures respectively to partially expose the surface of the semiconductor substrate.