Abstract: A method for forming a packaged integrated circuit device includes providing a semiconductor wafer having a plurality of integrated circuit devices, each integrated circuit device extending into the semiconductor wafer to a first depth, and grinding a backside of the silicon wafer to no more than the first depth. The method further includes forming a backside cut between the integrated circuit devices. The backside cut extends to within the first depth, but the backside cut does not extend completely through the semiconductor wafer. The backside cut exposes a plurality of edges of each of the integrated circuit devices. The method further includes depositing, on the backside of the wafer, a metallization layer on a bottom surface of the integrated circuit devices and on the edges.

Abstract: The present disclosure provides a semiconductor device package. The semiconductor device package includes an antenna layer, a first circuit layer and a second circuit layer. The antenna layer has a first coefficient of thermal expansion (CTE). The first circuit layer is disposed over the antenna layer. The first circuit layer has a second CTE. The second circuit layer is disposed over the antenna layer. The second circuit layer has a third CTE. A difference between the first CTE and the second CTE is less than a difference between the first CTE and the third CTE.

Abstract: A method includes forming a dielectric layer on a semiconductor workpiece, forming a first patterned layer of a first dipole material on the dielectric layer, and performing a first thermal drive-in operation at a first temperature to form a diffusion feature in a first portion of the dielectric layer beneath the first patterned layer. The method also includes forming a second patterned layer of a second dipole material, where a first section of the second patterned layer is on the diffusion feature and a second section of the second patterned layer is offset from the diffusion feature. The method further includes performing a second thermal drive-in operation at a second temperature, where the second temperature is less than the first temperature. The method additionally includes forming a gate electrode layer on the dielectric layer.

Abstract: A package is formed that encapsulates first and second components having respective first and second thickness differing from each other. Each component has lower surface provided with electrical contact pads and an upper surface opposite the lower surface. A volume of molding material encapsulates the first component. The package includes a set redistribution layers including a set of electrically-conductive interconnects surrounded by electrically-insulating material. The redistribution layers are disposed above the upper surface of the first component. The package includes one or more electrically conductive interconnects that pass through the redistribution layers to the lower surface of the first component; The second component is disposes at a location adjacent to the first component. A first portion of the second component is surrounded by the volume of molding material and a second portion of the second component is surrounded by one or more of the redistribution layers.

Abstract: A semiconductor device includes a first semiconductor layer below a second semiconductor layer; first and second gate dielectric layers surrounding the first and the second semiconductor layers, respectively; and a gate electrode surrounding both the first and the second gate dielectric layers. The first gate dielectric layer has a first top section above the first semiconductor layer and a first bottom section below the first semiconductor layer. The second gate dielectric layer has a second top section above the second semiconductor layer and a second bottom section below the second semiconductor layer. The first top section has a first thickness. The second top section has a second thickness. The second thickness is greater than the first thickness.

Abstract: An electronic device package and method of fabricating such a package includes a first and second components encapsulated in a volume of molding material. A surface of the first component is bonded to a surface of the second component. Upper and lower sets of redistribution lowers that include, respectively, first and second sets of conductive interconnects are formed on opposite sides of the molding material. A through-package interconnect passes through the volume of molding material and has ends that terminate, respectively, within the upper set of redistribution layers and within the lower set of redistribution layers.

Abstract: A semiconductor substrate structure and a method of manufacturing a semiconductor substrate structure are provided. The semiconductor substrate structure includes a substrate, an electronic device, and a filling material. The substrate defines a cavity. The electronic device is disposed in the cavity and spaced apart from the substrate by a gap. The filling material is disposed in the gap and covers a first region of an upper surface of the electronic device.

Abstract: A method of manufacturing a semiconductor device is provided. The method includes forming a redistribution layer (RDL) over a semiconductor die. A portion of the RDL contacts a die pad of the semiconductor die. A metal layer is formed on a top surface and sidewalls of the RDL and configured to encase the RDL. A non-conductive layer is formed over the metal layer and underlying RDL. An opening in the non-conductive layer is formed exposing a portion of the metal layer formed on the RDL. An under-bump metallization (UBM) is formed in the opening and conductively connected to the die pad by way of the metal layer and RDL.

Abstract: An electrically conductive structure of lithium battery mainly comprises a housing, a lithium-battery-core, a cover plate, a first-metal-plate and a second-metal-plate.

Abstract: A method for forming a packaged integrated circuit device includes providing a semiconductor wafer having a plurality of integrated circuit devices, each integrated circuit device extending into the semiconductor wafer to a first depth, and grinding a backside of the silicon wafer to no more than the first depth. The method further includes forming a backside cut between the integrated circuit devices. The backside cut extends to within the first depth, but the backside cut does not extend completely through the semiconductor wafer. The backside cut exposes a plurality of edges of each of the integrated circuit devices. The method further includes depositing, on the backside of the wafer, a metallization layer on a bottom surface of the integrated circuit devices and on the edges.

Abstract: A method of forming a semiconductor device is provided. The method includes encapsulating with an encapsulant at least a portion of a semiconductor die and a package substrate, the encapsulant including an additive selectively activated by way of a laser. A first opening is formed in the encapsulant, the first opening exposing a predetermined first portion of the package substrate. The additive is activated at the sidewalls of the first opening. A second opening is formed in the encapsulant, the second opening encircling the first opening and exposing a predetermined second portion of the package substrate. The additive is activated at the sidewalls the second opening. A conductive material is plated on the additive activated portions of the encapsulant.

Abstract: The subject application discloses a substrate. The substrate includes a first conductive layer, a first bonding layer, a first dielectric layer, and a conductive via. The first bonding layer is disposed on the first conductive layer. The first dielectric layer is disposed on the first bonding layer. The conductive via penetrates the first dielectric layer and is electrically connected with the first conductive layer.

Abstract: A method of speeding up a secure boot process and an electronic device using the method. The method includes the following. Whether a storage medium stores a pre-stored hash value corresponding to an image file for the secure boot process is determined. A hash value of the image file is calculated to determine whether the hash value matches the pre-stored hash value in response to the storage medium storing the pre-stored hash value. Firmware in the image file is executed to boot up the electronic device in response to the hash value matching the pre-stored hash value.

Abstract: A semiconductor device includes a first semiconductor layer below a second semiconductor layer; first and second gate dielectric layers surrounding the first and the second semiconductor layers, respectively; and a gate electrode surrounding both the first and the second gate dielectric layers. The first gate dielectric layer has a first top section above the first semiconductor layer and a first bottom section below the first semiconductor layer. The second gate dielectric layer has a second top section above the second semiconductor layer and a second bottom section below the second semiconductor layer. The first top section has a first thickness. The second top section has a second thickness. The second thickness is greater than the first thickness.

Abstract: The present disclosure provides a semiconductor device package. The semiconductor device package includes an antenna layer, a first circuit layer and a second circuit layer. The antenna layer has a first coefficient of thermal expansion (CTE). The first circuit layer is disposed over the antenna layer. The first circuit layer has a second CTE. The second circuit layer is disposed over the antenna layer. The second circuit layer has a third CTE. A difference between the first CTE and the second CTE is less than a difference between the first CTE and the third CTE.

Abstract: A circuit structure and an electronic structure are provided. The circuit structure includes a low-density conductive structure, a high-density conductive structure and an electrical connection structure. The high-density conductive structure is disposed on the low-density conductive structure. The electrical connection structure extends through the high-density conductive structure and is electrically connected to the low-density conductive structure. The electrical connection structure includes a shoulder portion.

Abstract: A method includes providing a structure having a first channel member and a second channel member over a substrate. The first channel member is located in a first region of the structure and the second channel member is located in a second region of the structure. The method also includes forming a first oxide layer over the first channel member and a second oxide layer over the second channel member, forming a first dielectric layer over the first oxide layer and a second dielectric layer over the second oxide layer, and forming a capping layer over the second dielectric layer but not over the first dielectric layer. The method further includes performing an annealing process to increase a thickness of the second oxide layer under the capping layer.

Abstract: A capacitor structure includes a first metal layer, a first metal oxide layer, a second metal oxide layer, a first conductive member, a second conductive member and a metal composite structure. The first metal layer has a first surface and a second surface opposite the first surface. The first metal oxide layer is formed on the first surface of the first metal layer. The second metal oxide layer is formed on the second surface of the first metal layer. The first conductive member penetrates through the capacitor structure and is electrically isolated from the first metal layer. The second conductive member is electrically connected to the first metal layer. The metal composite structure is disposed between the second conductive member and the first metal layer.

Abstract: An IC package includes one or more microelectronic devices, a plurality of package bumps disposed at a first side, and a metal structure electrically connecting at least a first device contact pad of a first microelectronic device and at least a first package bump of the plurality of package bumps. The metal structure includes an RDL trace extending between a first region aligned with the first device contact pad and a second region aligned with the first package bump, wherein the first package bump is mechanically and electrically connected directly to the second region of the RDL trace. The metal structure further includes a first via extending between the first region of the RDL trace and the first device contact pad and further includes a set of one or more support studs extending from the second region to a support surface facing the first side.

Abstract: A method of forming a semiconductor device is provided. The method includes placing a semiconductor die and a leadframe on a carrier substrate. The semiconductor die includes a plurality of bond pads and the leadframe includes a plurality of leads. A first lead of the plurality of leads has a proximal end affixed to a first bond pad of the plurality of bond pads and a distal end placed on the carrier substrate. At least a portion of the semiconductor die and the leadframe is encapsulated with an encapsulant. The carrier substrate is separated from a first major side of the encapsulated semiconductor die and leadframe exposing a distal end portion of the first lead. A package substrate is applied on the first major side.