Patents by Inventor Wen-Hung Huang

Wen-Hung Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor package structures, semiconductor device packages and methods of manufacturing the same
    Patent number: 11322471
    Abstract: A semiconductor package structure includes a first substrate, a second substrate, a first redistribution layer, and a first reconnection layer. The first substrate may have a first surface. The second substrate can be spaced apart from the first substrate with a gap and may have a second surface. The first redistribution layer can be disposed between the first redistribution layer and the gap. The first substrate can be electrically connected to the second substrate via the first reconnection layer.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: May 3, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Wen Hung Huang
  • Semiconductor device package
    Patent number: 11309295
    Abstract: A semiconductor device package includes a first passive component having a first surface and a second passive component having a second surface facing the first surface of the first passive component. The first surface has a recessing portion and the second surface includes a protruding portion within the recessing portion of the first surface of the first passive component. A contour of the protruding portion and a contour of the recessing portion are substantially matched. A method of manufacturing a semiconductor device package is also disclosed.
    Type: Grant
    Filed: August 26, 2019
    Date of Patent: April 19, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Wen Hung Huang, Wen Chieh Yang
  • Semiconductor device package
    Patent number: 11309264
    Abstract: The present disclosure provides a semiconductor device package. The semiconductor device package includes an antenna layer, a first circuit layer and a second circuit layer. The antenna layer has a first coefficient of thermal expansion (CTE). The first circuit layer is disposed over the antenna layer. The first circuit layer has a second CTE. The second circuit layer is disposed over the antenna layer. The second circuit layer has a third CTE. A difference between the first CTE and the second CTE is less than a difference between the first CTE and the third CTE.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: April 19, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Wen Hung Huang
  • SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20220115338
    Abstract: The present disclosure provides a semiconductor device package. The semiconductor device package includes a first conductive component, a second conductive component, a planarization layer and an antenna layer. The second conductive component is disposed adjacent to the first conductive component. The second conductive component and the first conductive component have different thicknesses. The planarization layer is disposed on the first conductive component. The antenna layer is disposed on the first conductive component and the second conductive component.
    Type: Application
    Filed: October 9, 2020
    Publication date: April 14, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Wen Hung HUANG
  • Device structure and method for manufacturing the same
    Patent number: 11302619
    Abstract: A device structure includes a stacked structure, a dielectric material, and an electrode via. The stacked structure includes a first metal oxide layer, a second metal oxide layer and a metal layer. The second metal oxide layer is opposite to the first metal oxide layer. The metal layer is interposed between the first metal oxide layer and the second metal oxide layer. The dielectric material extends through the first metal oxide layer. The electrode via extends through the dielectric material and electrically connected to the metal layer.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: April 12, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Wen Hung Huang
  • Decision feedback equalization embedded in a slicer
    Patent number: 11271783
    Abstract: An apparatus and method for providing a decision feedback equalizer are disclosed herein. In some embodiments, a method and apparatus for reduction of inter-symbol interference (ISI) caused by communication channel impairments is disclosed. In some embodiments, a decision feedback equalizer includes a plurality of delay latches connected in series, a slicer circuit configured to receive an input signal from a communication channel and delayed feedback signals from the plurality of delay latches and determine a logical state of the received input signal, wherein the slicer circuit further comprises a dynamic threshold voltage calibration circuit configured to regulate a current flow between output nodes of the slicer circuit and ground based on the received delayed feedback signal and impulse response coefficients of the communication channel.
    Type: Grant
    Filed: December 9, 2020
    Date of Patent: March 8, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shu-Chun Yang, Wen-Hung Huang
  • SUBSTRATE STRUCTURES AND METHODS FOR FORMING THE SAME AND SEMICONDUCTOR PACKAGE STRUCTURES
    Publication number: 20220068783
    Abstract: A substrate structure and a method for manufacturing the same are provided. The substrate structure includes a first conductive layer, a dielectric layer, a second conductive layer and a connection layer. The dielectric layer is disposed on the first conductive layer. The dielectric layer defines an opening exposing the first conductive layer. The second conductive layer is disposed on the dielectric layer. The connection layer extends from an upper surface of the first conductive layer to a lateral surface of the second conductive layer. A surface roughness of an upper surface of the second conductive layer ranges from about 0.5 ?m to about 1.25 ?m.
    Type: Application
    Filed: August 31, 2020
    Publication date: March 3, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Wen Hung HUANG
  • Semiconductor devices, semiconductor device packages and method for manufacturing the same
    Patent number: 11264340
    Abstract: A capacitor structure includes a first metal layer, a first metal oxide layer, a second metal oxide layer, a first conductive member, a second conductive member and a metal composite structure. The first metal layer has a first surface and a second surface opposite the first surface. The first metal oxide layer is formed on the first surface of the first metal layer. The second metal oxide layer is formed on the second surface of the first metal layer. The first conductive member penetrates through the capacitor structure and is electrically isolated from the first metal layer. The second conductive member is electrically connected to the first metal layer. The metal composite structure is disposed between the second conductive member and the first metal layer.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: March 1, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Wen Hung Huang
  • WIRING STRUCTURE AND METHOD FOR MANUFACTURING THE SAME
    Publication number: 20220037242
    Abstract: A wiring structure and a method for manufacturing the same are provided. The wiring structure includes a conductive structure and at least one conductive through via. The conductive structure includes a plurality of dielectric layers, a plurality of circuit layers in contact with the dielectric layers, and a plurality of dam portions in contact with the dielectric layers. The dam portions are substantially arranged in a row and spaced apart from one another. The conductive through via extends through the dam portions.
    Type: Application
    Filed: July 31, 2020
    Publication date: February 3, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Wen Hung HUANG, Min Lung HUANG
  • WIRING STRUCTURE AND METHOD FOR MANUFACTURING THE SAME
    Publication number: 20220020674
    Abstract: A wiring structure and a method for manufacturing the same are provided. The wiring structure includes a conductive structure and at least one conductive through via. The conductive structure includes a plurality of dielectric layers and a plurality of circuit layers in contact with the dielectric layers. The conductive through via extends through the conductive structure. The conductive through via is a monolithic structure, and includes a main portion and an extending portion protruding from the main portion.
    Type: Application
    Filed: July 16, 2020
    Publication date: January 20, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Wen Hung HUANG
  • SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20220005771
    Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes an antenna zone and a routing zone. The routing zone is disposed on the antenna zone, where the antenna zone includes a first insulation layer and two or more second insulation layer and a thickness of the first insulation layer is different from that of the second insulation layer.
    Type: Application
    Filed: September 20, 2021
    Publication date: January 6, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Wen Hung HUANG, Yan Wen CHUNG, Wei Chu SUN
  • Semiconductor device package and method for manufacturing the same
    Patent number: 11211325
    Abstract: A semiconductor package may include a first substrate and a second substrate, a redistribution layer (RDL), a first conductive via and a second conductive via. The first substrate has a first surface and a second surface opposite to the first surface. The second substrate has a first surface and a second surface opposite to the first surface. The RDL is disposed on the first surface of the first substrate and the first surface of the second substrate. The first conductive via passes through the RDL and is electrically connected to the first substrate. The second conductive via passes through the RDL and is electrically connected to the second substrate.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: December 28, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Wen Hung Huang, Yan Wen Chung, Min Lung Huang
  • Wiring structure and method for manufacturing the same
    Patent number: 11211316
    Abstract: A wiring structure and a method for manufacturing the same are provided. The wiring structure includes a conductive structure and at least one conductive through via. The conductive structure includes a plurality of dielectric layers and a plurality of circuit layers in contact with the dielectric layers. The conductive through via extends through at least a portion of the conductive structure. At least one of the circuit layers includes a first portion in contact with the conductive through via and a second portion in contact with the dielectric layer. A surface roughness of the first portion of the circuit layer is greater than a surface roughness of the second portion of the circuit layer.
    Type: Grant
    Filed: September 23, 2020
    Date of Patent: December 28, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Wen Hung Huang
  • Wiring structure having at least one sub-unit
    Patent number: 11211299
    Abstract: A wiring structure includes a first unit, a second unit, a first insulation wall, a first redistribution layer and a third unit. The first unit is disposed at a first elevation and having a first circuit layer and a first dielectric layer surrounding the first circuit layer. The second unit is disposed at the first elevation and having a second circuit layer and a second dielectric layer surrounding the second circuit layer. The first insulation wall is disposed between the first unit and the second unit. The first redistribution layer is disposed on the first unit and the second unit, and electrically connected between the first unit and the second unit. The third unit is disposed on the first redistribution layer and having a third circuit layer and a third dielectric layer surrounding the third circuit layer.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: December 28, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Wen Hung Huang
  • PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME
    Publication number: 20210343632
    Abstract: A package structure and a method for manufacturing a package structure are provided. The package structure includes a substrate, at least one redistribution structure, at least one electronic component and at least one semiconductor die. The substrate has a first surface and a second surface opposite to the first surface. The at least one redistribution structure is disposed on the first surface of the substrate. The at least one electronic component is disposed on the first surface of the substrate. The at least one semiconductor die is disposed on the at least one redistribution structure and electrically connected to the at least one electronic component through the substrate.
    Type: Application
    Filed: April 29, 2020
    Publication date: November 4, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Wen Hung HUANG
  • Wiring structure and method for manufacturing the same
    Patent number: 11139232
    Abstract: A wiring structure and a method for manufacturing a wiring structure are provided. The wiring structure includes a first conductive structure, a second conductive structure, a dent structure and an adhesion layer. The first conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. The second conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. The dent structure is attached to the first conductive structure. The adhesion layer is interposed between the first conductive structure and the second conductive structure to bond the first conductive structure and the second conductive structure together. A periphery portion of the adhesion layer is disposed in a gap between the dent structure and the second conductive structure.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: October 5, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Wen Hung Huang
  • SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20210305180
    Abstract: The present disclosure provides a semiconductor device package. The semiconductor device package includes an antenna layer, a first circuit layer and a second circuit layer. The antenna layer has a first coefficient of thermal expansion (CTE). The first circuit layer is disposed over the antenna layer. The first circuit layer has a second CTE. The second circuit layer is disposed over the antenna layer. The second circuit layer has a third CTE. A difference between the first CTE and the second CTE is less than a difference between the first CTE and the third CTE.
    Type: Application
    Filed: March 27, 2020
    Publication date: September 30, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Wen Hung HUANG
  • WIRING STRUCTURE AND METHOD FOR MANUFACTURING THE SAME
    Publication number: 20210296230
    Abstract: A wiring structure and a method for manufacturing the same are provided. The wiring structure includes an upper conductive structure, a lower conductive structure and a redistribution structure. The upper conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. The lower conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. The redistribution structure is disposed between the upper conductive structure and the lower conductive structure to electrically connect the upper conductive structure and the lower conductive structure. The redistribution structure includes a dielectric structure and a redistribution layer embedded in the dielectric structure. The redistribution layer includes at least one circuit layer.
    Type: Application
    Filed: March 17, 2020
    Publication date: September 23, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Wen Hung HUANG
  • Semiconductor device and method of manufacturing the same
    Patent number: 11127697
    Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes an antenna zone and a routing zone. The routing zone is disposed on the antenna zone, where the antenna zone includes a first insulation layer and two or more second insulation layer and a thickness of the first insulation layer is different from that of the second insulation layer.
    Type: Grant
    Filed: July 10, 2019
    Date of Patent: September 21, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Wen Hung Huang, Yan Wen Chung, Wei Chu Sun
  • WIRING STRUCTURE AND METHOD FOR MANUFACTURING THE SAME
    Publication number: 20210280505
    Abstract: A wiring structure and a method for manufacturing a wiring structure are provided. The wiring structure includes a first conductive structure, a second conductive structure, a dent structure and an adhesion layer. The first conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. The second conductive structure includes at least one dielectric layer and at least one circuit layer in contact with the dielectric layer. The dent structure is attached to the first conductive structure. The adhesion layer is interposed between the first conductive structure and the second conductive structure to bond the first conductive structure and the second conductive structure together. A periphery portion of the adhesion layer is disposed in a gap between the dent structure and the second conductive structure.
    Type: Application
    Filed: March 6, 2020
    Publication date: September 9, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Wen Hung HUANG