Abstract: A semiconductor device includes a first semiconductor layer below a second semiconductor layer; first and second gate dielectric layers surrounding the first and the second semiconductor layers, respectively; and a gate electrode surrounding both the first and the second gate dielectric layers. The first gate dielectric layer has a first top section above the first semiconductor layer and a first bottom section below the first semiconductor layer. The second gate dielectric layer has a second top section above the second semiconductor layer and a second bottom section below the second semiconductor layer. The first top section has a first thickness. The second top section has a second thickness. The second thickness is greater than the first thickness.

Abstract: A method for manufacturing a packaged integrated circuit device includes providing a semiconductor wafer having a plurality of integrated circuit devices. Each integrated circuit device extends into the semiconductor wafer to a first depth. Prior to singulation of the integrated circuit devices on the semiconductor wafer, the method further includes forming a cut between the integrated circuit devices. The cut extends to at least the first depth, but does not extend completely through the semiconductor wafer. The cut exposes a plurality of edges of each of the integrated circuit devices. The method further includes depositing, on each integrated circuit device, a passivation layer on a top surface and on the edges.

Abstract: A method for forming a packaged integrated circuit device includes providing a semiconductor wafer having a plurality of integrated circuit devices, each integrated circuit device extending into the semiconductor wafer to a first depth, and grinding a backside of the silicon wafer to no more than the first depth. The method further includes forming a backside cut between the integrated circuit devices. The backside cut extends to within the first depth, but the backside cut does not extend completely through the semiconductor wafer. The backside cut exposes a plurality of edges of each of the integrated circuit devices. The method further includes depositing, on the backside of the wafer, a metallization layer on a bottom surface of the integrated circuit devices and on the edges.

Abstract: Embodiments of systems and methods for detecting short circuits in a load are described. In an illustrative, non-limiting embodiment, a short circuit detection system includes a first circuit, a second circuit, and a controller. The first circuit has an output and an input coupled to a load and an auxiliary power source through a resistor, while the second circuit is configured to enable an output of the short circuit detection circuit for a specified period of time following application of auxiliary power at the auxiliary power source. The controller includes computer-executable instructions to monitor the output of the first circuit, and allow or disallow a main power source from powering the load based upon whether a short circuit condition exists.

Abstract: A method includes forming a first gate dielectric, a second gate dielectric, and a third gate dielectric over a first semiconductor region, a second semiconductor region, and a third semiconductor region, respectively. The method further includes depositing a first lanthanum-containing layer overlapping the first gate dielectric, and depositing a second lanthanum-containing layer overlapping the second gate dielectric. The second lanthanum-containing layer is thinner than the first lanthanum-containing layer. An anneal process is then performed to drive lanthanum in the first lanthanum-containing layer and the second lanthanum-containing layer into the first gate dielectric and the second gate dielectric, respectively. During the anneal process, the third gate dielectric is free from lanthanum-containing layers thereon.

Abstract: An apparatus and method for providing a decision feedback equalizer are disclosed herein. In some embodiments, a method and apparatus for reduction of inter-symbol interference (ISI) caused by communication channel impairments is disclosed. In some embodiments, a decision feedback equalizer includes a plurality of delay latches connected in series, a slicer circuit configured to receive an input signal from a communication channel and delayed feedback signals from the plurality of delay latches and determine a logical state of the received input signal, wherein the slicer circuit further comprises a dynamic threshold voltage calibration circuit configured to regulate a current flow between output nodes of the slicer circuit and ground based on the received delayed feedback signal and impulse response coefficients of the communication channel.

Abstract: A packaging semiconductor device, such as a fan-out Wafer-Level Packaging (FOWLP) device, is fabricated by providing a semiconductor device (20) having conductive patterns (22) disposed on a first surface and then forming, on the conductive patterns, photoresist islands (24) having a first predetermined shape defined by a first critical width dimension and a minimum height dimension so that a subsequently-formed dielectric polymer layer (26) surrounds but does not cover each photoresist island (24), thereby allowing each photoresist island to be selectively removed from the one or more conductive patterns to form one or more via openings (28) in the dielectric polymer layer such that each via opening has a second predetermined shape which matches at least part of the first predetermined shape of the photoresist islands.

Abstract: Embodiments of systems and methods for detecting short circuits in a load are described. In an illustrative, non-limiting embodiment, a short circuit detection system includes a first circuit, a second circuit, and a controller. The first circuit has an output and an input coupled to a load and an auxiliary power source through a resistor, while the second circuit is configured to enable an output of the short circuit detection circuit for a specified period of time following application of auxiliary power at the auxiliary power source. The controller includes computer-executable instructions to monitor the output of the first circuit, and allow or disallow a main power source from powering the load based upon whether a short circuit condition exists.

Abstract: The subject application discloses a substrate. The substrate includes a first conductive layer, a first bonding layer, a first dielectric layer, and a conductive via. The first bonding layer is disposed on the first conductive layer. The first dielectric layer is disposed on the first bonding layer. The conductive via penetrates the first dielectric layer and is electrically connected with the first conductive layer.

Abstract: A semiconductor device includes a stack of semiconductor layers vertically arranged above a semiconductor base structure, a gate dielectric layer having portions each surrounding one of the semiconductor layers, and a gate electrode surrounding the gate dielectric layer. Each portion of the gate dielectric layer has a top section above the respective semiconductor layer and a bottom section below the semiconductor layer. The top section has a top thickness along a vertical direction perpendicular to a top surface of the semiconductor base structure; and the bottom section has a bottom thickness along the vertical direction. The top thickness is greater than the bottom thickness.

Abstract: A method includes providing a structure having a first channel member and a second channel member over a substrate. The first channel member is located in a first region of the structure and the second channel member is located in a second region of the structure. The method also includes forming a first oxide layer over the first channel member and a second oxide layer over the second channel member, forming a first dielectric layer over the first oxide layer and a second dielectric layer over the second oxide layer, and forming a capping layer over the second dielectric layer but not over the first dielectric layer. The method further includes performing an annealing process to increase a thickness of the second oxide layer under the capping layer.

Abstract: An n-type field effect transistor includes semiconductor channel members vertically stacked over a substrate, a gate dielectric layer wrapping around each of the semiconductor channel members, and a work function layer disposed over the gate dielectric layer. The work function layer wraps around each of the semiconductor channel members. The n-type field effect transistor also includes a WF isolation layer disposed over the WF layer and a gate metal fill layer disposed over the WF isolation layer. The WF isolation layer fills gaps between adjacent semiconductor channel members.

Abstract: A hot-swap circuit for providing soft start and overcurrent protection to an electronic circuit may include a controller and a timer. The controller may be configured to sense an electrical current associated with the hot-swap circuit, based on the electrical current sensed, perform current limiting of the electrical current to minimize inrush current to the electronic circuit, and disable the electrical current from flowing to the electronic circuit in response to the electrical current exceeding an overcurrent threshold for longer than a duration of a fault timer. The timer circuit may be configured to, for a period of time after enabling of the hot-swap circuit, cause the duration of the fault timer to be a first duration, and after the period of time, cause the duration of the fault timer to be a second duration significantly shorter than the first duration.

Abstract: A circuit structure and an electronic structure are provided. The circuit structure includes a low-density conductive structure, a high-density conductive structure and an electrical connection structure. The high-density conductive structure is disposed on the low-density conductive structure. The electrical connection structure extends through the high-density conductive structure and is electrically connected to the low-density conductive structure. The electrical connection structure includes a shoulder portion.

Abstract: A package structure and a method for manufacturing a package structure are provided. The package structure includes a substrate, at least one redistribution structure, at least one electronic component and at least one semiconductor die. The substrate has a first surface and a second surface opposite to the first surface. The at least one redistribution structure is disposed on the first surface of the substrate. The at least one electronic component is disposed on the first surface of the substrate. The at least one semiconductor die is disposed on the at least one redistribution structure and electrically connected to the at least one electronic component through the substrate.

Abstract: Packaged semiconductor devices are disclosed, comprising: a semiconductor die having a top major surface with a plurality of contact pads thereon, and four sides, wherein the sides are stepped such that a lower portion of each side extends laterally beyond a respective upper portion; encapsulating material encapsulating the top major surface and the upper portion of each of the sides wherein the semiconductor die is exposed at the lower portion of each of the sides; a contact-redistribution structure on the encapsulating material over the top major surface of the semiconductor die; a plurality of metallic studs extending through the encapsulating material, and providing electrical contact between the contact pads and the contact-redistribution structure. Corresponding methods are also disclosed.

Abstract: The current disclosure describes techniques for individually selecting the number of channel strips for a device. The channel strips are selected by defining a three-dimensional active region that include a surface active area and a depth/height. Semiconductor strips in the active region are selected as channel strips. Semiconductor strips contained in the active region will be configured to be channel strips. Semiconductor strips not included in the active region are not selected as channel strips and are separated from source/drain structures by an auxiliary buffer layer.

Abstract: A wiring structure includes an upper conductive structure, a lower conductive structure, an intermediate layer and at least one through via. The upper conductive structure includes at least one upper dielectric layer and at least one upper circuit layer in contact with the upper dielectric layer. The lower conductive structure includes at least one lower dielectric layer and at least one lower circuit layer in contact with the lower dielectric layer. The intermediate layer is disposed between the upper conductive structure and the lower conductive structure and bonds the upper conductive structure and the lower conductive structure together. The through via extends through the upper conductive structure, the intermediate layer and the lower conductive structure.

Abstract: A packaging semiconductor device, such as a fan-out Wafer-Level Packaging (FOWLP) device, is fabricated by providing a semiconductor device (20) having conductive patterns (22) disposed on a first surface and then forming, on the conductive patterns, photoresist islands (24) having a first predetermined shape defined by a first critical width dimension and a minimum height dimension so that a subsequently-formed dielectric polymer layer (26) surrounds but does not cover each photoresist island (24), thereby allowing each photoresist island to be selectively removed from the one or more conductive patterns to form one or more via openings (28) in the dielectric polymer layer such that each via opening has a second predetermined shape which matches at least part of the first predetermined shape of the photoresist islands.

Abstract: A MOSFET structure including stacked vertically isolated MOSFETs and a method for forming the same are disclosed.