Abstract: A semiconductor device with an identification structure is provided. The semiconductor device includes a substrate and a metallization structure over the substrate. The metallization structure includes an interconnection region having a plurality of metal layers and an identification region isolated from the interconnection region. The identification region has an identification structure leveled with one of the metal layer. The identification structure includes at least one exposing recess and at least one exposing fuse. A method for manufacturing a semiconductor device with an identification structure and a method for tracing a production information of a semiconductor device are also provided.

Abstract: A memory device includes a memory die, a non-volatile memory circuit, and a logic die. The memory die includes a first memory space and a second memory space. The non-volatile memory circuit stores a repair table file corresponding to the first memory space. The logic die is coupled to the memory die and the non-volatile memory. The logic die selectively accesses the first memory space or the second memory space of the memory die according a comparing result of an input address and the repair table file. The memory die and is different from the logic die.

Abstract: A semiconductor package includes a plurality of integrated circuit (IC) substrates and a conductive structure. The IC substrates are stacked one above another. The conductive structure penetrates through the IC substrates. Each of the IC substrates includes an identification circuit coupled to the conductive structure. Each identification circuit is configured to identify a corresponding IC substrate by receiving an input signal from the conductive structure and accordingly generating an identifier of the corresponding IC substrate.

Abstract: A method for bonding tested wafers is provided. The method includes the following operations. A first wafer having a first surface is received, and the first wafer includes a test pad and a conductive pad at the first surface of the first wafer and the test pad has a recess caused by a test probe and the conductive pad is electrically connected to the test pad. The first surface of the first wafer is planarized. A first hybrid bonding layer is formed over the first surface of the first wafer. The first wafer and a second wafer are bonded to connect the first hybrid bonding layer and a second hybrid bonding layer on the second water. A semiconductor structure and a method for testing pre-bonded wafers are also provided.

Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a first semiconductor structure, a dielectric bonding structure, a second semiconductor structure, and a through via structure. The first semiconductor structure includes a first substrate and a first back-end-of-line (BEOL) structure over the first substrate. The dielectric bonding structure is over the first semiconductor structure. The second semiconductor structure is over the dielectric bonding structure. The second semiconductor structure includes a second BEOL structure over the dielectric bonding structure and a second substrate over the second BEOL structure. The through via structure penetrates the second semiconductor structure and the dielectric bonding structure to connect the first BEOL structure and the second BEOL structure. A method for forming a semiconductor package structure is also provided.

Abstract: A circuit assembly includes an IC die and a stack of capacitor dies. The IC die has a first hybrid bonding layer. The stack of capacitor dies includes a first capacitor die and a second capacitor die. The first capacitor die has a second hybrid bonding layer in contact with the first hybrid bonding layer. The second capacitor die is stacked over the first capacitor die. The first capacitor die has a third hybrid bonding layer. The second capacitor die has a fourth hybrid bonding layer coupled to the third hybrid bonding layer. The second capacitor die has a first side and a second side, the fourth hybrid bonding layer is formed on the second side, a plurality of conductive vias is formed on the first side, and the second capacitor die further comprises a plurality of interface bumps electrically connecting to the conductive vias.

Abstract: A circuit assembly includes an integrated circuit (IC) die and a capacitor die. The IC die has a first hybrid bonding layer. The capacitor die is stacked with the IC die, and is configured to include a capacitor coupled to the IC die, and has a second hybrid bonding layer in contact with the first hybrid bonding layer; wherein the IC die is electrically coupled to the capacitor die through the first hybrid bonding layer and the second hybrid bonding layer.

Abstract: A method for manufacturing a plurality of semiconductor structures is provided. The method includes the operations as follows. A first hybrid bonding layer is formed over a first wafer including a plurality of first memory structures. A second hybrid bonding layer is formed over a second wafer including a plurality of control circuit structures. The memory structures and the control circuit structures are in contact with the first and the second hybrid bonding layers, respectively. The first wafer and the second wafer are bonded through a first hybrid bonding operation to connect the first and the second hybrid bonding layers, thereby obtaining a first bonded wafer. At least the first wafer, the second wafer, the first hybrid bonding structure, and the second hybrid bonding structure are singulated to obtain the plurality of semiconductor structures. A method for manufacturing a system in package (SiP) is also provided.

Abstract: A switched mode power supply (SMPS) includes a first switch, a second switch connected, at a switching node, in series with the first switch, and an inductor coupled between the switching node and an output node for providing an inductor current, at the output node. The SMPS also includes an oscillator circuit for providing a clock signal characterized by an oscillating frequency, an adaptive minimum duty-cycle circuit configured to receive an error voltage signal and to generate a current signal to vary the oscillating frequency of the clock signal in response to the error voltage signal, wherein the error voltage signal is based on an output signal at the output node, and a pulse-width modulation (PWM) circuit configured to receive the error voltage signal and the clock signal and to provide a switching control signal to control the first switch and the second switch.

Abstract: A method for a switched mode power supply (SMPS) includes providing an error voltage signal based on a difference between a sampled output voltage of the SMPS and a target voltage, and generating a clock signal characterized by an oscillating frequency; generating a switching control signal based on the error voltage signal and the clock signal using pulse-width modulation (PWM). The method further includes varying the oscillating frequency of the clock signal according to the error voltage signal in a current generating circuit, and applying the switching control signal to control the power switches of the SMPS.

Abstract: A display controller includes a first chip and a second chip. The first chip is configured to control a display device. The second chip is externally coupled to the first chip, and configured to be a random access memory and. The first chip is further configured to provide a first supply power to the second chip and to access the second chip during the controlling of the display device.

Abstract: An interface of a memory circuit includes a chip enable terminal, at least one data terminal, and a data strobe terminal. The chip enable terminal receives a chip enable signal that varies between a first high voltage and a low voltage. The at least one data terminal receives a first data signal that varies between a second high voltage and the low voltage during a command phase, and transmits or receives a second data signal during a data phase. The data strobe terminal receives a first data strobe signal that periodically varies between the second high voltage and the low voltage during the command phase, and transmits or receives a second data strobe signal that swings periodically during the data phase. During a transition interval between the command phase and the data phase, the data strobe terminal stops receiving or transmitting data strobe signals that swing periodically.

Abstract: A method of generating, from a first thermal model describing the individual thermal behaviour of an electrical machine and a second thermal model describing the individual thermal behaviour of a device, a composite thermal model describing the thermal behaviour of a system having the electrical machine connected to the device, the method including: a) connecting at least one geometric entity of one of the first thermal model and the second thermal model to a plurality of geometric entities of the other one of the first thermal model and the second thermal model, each connection including at least one of a heat source and a thermal impedance, wherein the first thermal model and the second thermal model connected to each other form an initial composite thermal model, b) comparing measured temperatures with corresponding estimated temperatures obtained from the initial composite thermal model, and in case an estimated temperature deviates with more than a threshold value from a measured temperature, c) adjustin

Abstract: A method of operating a microelectronic package includes a processing device stacking vertically with at least one memory device. The method includes a step of: reading data stored in a plurality of memory cells of a plurality of memory units of the memory device, with the processing device, with a plurality of signal channels each of which is dedicated to transmit signals from the processing device to one of the memory units and vice versa.

Abstract: A memory device includes one or more memory blocks. Each memory block includes a plurality of first sense amplifier circuits, a plurality of row segments, and a plurality of row decoders. The row segments and the first sense amplifier circuits are arranged alternately along a first direction. Each row segment includes a plurality of memory cells arranged in rows and columns. Each column of memory cells extends in the first direction. The row segments are divided into N groups of row segments, and N is greater than one. The row decoders are coupled to the row segments respectively, and divided into N groups of row decoders.

Abstract: A switched mode power supply (SMPS) includes a first switch, a second switch connected, at a switching node, in series with the first switch, and an inductor coupled between the switching node and an output node for providing an inductor current, at the output node. The SMPS also includes an oscillator circuit for providing a clock signal characterized by an oscillating frequency, an adaptive minimum duty-cycle circuit configured to receive an error voltage signal and to generate a current signal to vary the oscillating frequency of the clock signal in response to the error voltage signal, wherein the error voltage signal is based on an output signal at the output node, and a pulse-width modulation (PWM) circuit configured to receive the error voltage signal and the clock signal and to provide a switching control signal to control the first switch and the second switch.

Abstract: An interface of a memory circuit includes a chip enable terminal, at least one data terminal, and a data strobe terminal. The chip enable terminal receives a chip enable signal that varies between a first high voltage and a low voltage for enabling the memory circuit. The at least one data terminal receives at least one first data signal that varies between a second high voltage and the low voltage. The data strobe terminal receives a first data strobe signal that periodically varies between the second high voltage and the low voltage. The first data strobe signal is synchronized with the at least one first data signal, and is arranged to latch and sample the at least one first data signal. The first high voltage is higher than the second high voltage, and the second high voltage is higher than the low voltage.

Abstract: A method for manufacturing a plurality of semiconductor structures is provided. The method includes the operations as follows. A first hybrid bonding layer is formed over a first wafer including a plurality of first memory structures. A second hybrid bonding layer is formed over a second wafer including a plurality of control circuit structures. The memory structures and the control circuit structures are in contact with the first and the second hybrid bonding layers, respectively. The first wafer and the second wafer are bonded through a first hybrid bonding operation to connect the first and the second hybrid bonding layers, thereby obtaining a first bonded wafer. At least the first wafer, the second wafer, the first hybrid bonding structure, and the second hybrid bonding structure are singulated to obtain the plurality of semiconductor structures. A method for manufacturing a system in package (SiP) is also provided.

Abstract: A method of monitoring an electrical machine, wherein the method includes: a) obtaining temperature measurement values of the temperature at a plurality of locations of the electrical machine, b) obtaining estimated temperatures at the plurality of locations given by a thermal model of the electrical machine, the thermal model including initial weight parameter values, c) minimizing a difference between the temperature measurement values and the estimated temperatures by finding optimal weight parameter values, d) storing the initial weight parameter values to thereby obtain a storage of used weight parameter values, and updating the optimal weight parameter values as new initial weight parameter values, and repeating steps a)-d) over and over during operation of the electrical machine.

Abstract: A DRAM chiplet structure is provided. The DRAM chiplet structure includes a first hybrid bonding structure, a DRAM interface structure, and a first DRAM core structure. The first hybrid bonding structure has a first surface and a second surface. The DRAM interface structure is in contact with the first surface of the first hybrid bonding structure. The first DRAM core structure is in contact with the second surface of the first hybrid bonding structure. The DRAM interface structure is electrically connected to the first DRAM core structure through the first hybrid bonding structure.