Abstract: A capacitor device includes: a substrate; an insulation film, disposed on the substrate; at least one capacitor unit cell, being covered by the insulation film on the substrate, the at least one capacitor unit cell having at least one first electrode and at least one second electrode disposed over the first electrode; an exposed conductive layer, disposed on the at least one capacitor unit cell and the insulation film, the exposed conductive layer having a first conductive pad formed on a first side of the exposed conductive layer and a second conductive pad formed on a second side different from the first side; wherein the first conductive pad and the second conductive pad are electrically connected to the at least one first electrodes and the at least one second electrodes of the at least one capacitor unit cell respectively.

Abstract: In one embodiment, a device is described for using ferroelectric material in a memory cell. In another embodiment, a method of operating a ferroelectric memory cell is described. Other embodiments are likewise described.

Abstract: A method of assembling a microelectronic package includes the step of: stacking a processing device vertically with at least one memory device and electrically connecting the processing device to a plurality of conductive interconnects of one of the at least one memory device, wherein each of the at least one memory device includes: a substrate, presenting a front surface and a back surface; and a plurality of memory units formed on the front surface, each of which comprises a plurality of memory cells and the conductive interconnects electrically connected to the memory cells; and arranging the conductive interconnects to contribute to a plurality of signal channels each of which dedicated to transmit signals from the processing device to one of the memory units and vice versa.

Abstract: A circuit assembly includes an integrated circuit (IC) die and a first capacitor die. The IC die provides an IC and includes a plurality of first conductive pads. The first capacitor die provides a plurality of capacitors, and includes a plurality of second conductive pads at the first side and a plurality of conductive vias at the second side. At least one of the second conductive pads electrically connects to the capacitors. The conductive vias is adapted to form a plurality of external signal connections of the IC die and the first capacitor die. The IC die is stacked with the first capacitor die in such a way that the first conductive pads electrically connect to the second conductive pads, and surfaces of the IC die and the first capacitor die attaching to each other are substantially of the same size.

Abstract: A method for manufacturing a semiconductor structures is provided. The method includes forming a first hybrid bonding layer over a first wafer having a logic structure, forming a second hybrid bonding layer over a second wafer having a first capacitor structure, bonding the first wafer and the second wafer through a hybrid bonding operation to connect the first hybrid bonding layer and the second hybrid bonding layer, thereby obtaining a first bonded wafer, and the first capacitor structure is electrically connected to the logic structure through the first hybrid bonding layer and the second hybrid bonding layer, and singulating the first bonded wafer to obtain a plurality of semiconductor structures.

Abstract: This disclosure relates to a multiphase converter design with multi-path phase management circuit and output logic. The phase management circuit and output logic can be employed to implement phase adding and shedding operations based on input and output current information and based on control signals for a power stage of the converter. In some examples, the design employs an estimate of an average output current based on a current at an input of the converter for phase control. In additional examples, the design employs cycle-by-cycle current limit and maximum duty-cycle signals to enable phase quickly during load transient. In further examples, the design employs low input and output-current sensed signals for efficient phase shedding and power saving. The design herein improves an overall accuracy of phase adding and shedding, load transient response performance, an operational efficiency and thermal performance of multiphase converter.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a first hybrid bonding structure, a memory structure, and a control circuit structure. The first hybrid bonding layer includes a first surface and a second surface. The memory structure is in contact with the first surface. The control circuit structure is configured to control the memory structure. The control circuit structure is in contact with the second surface. A system in package (SiP) structure and a method for manufacturing a plurality of semiconductor structures are also provided.

Abstract: The present disclosure relates to a neural network artificial intelligence chip and a method for forming the same. The neural network artificial intelligence chip includes: a storage circuit, that includes a plurality of storage blocks; and a calculation circuit, that includes a plurality of logic units, the logic units being correspondingly coupled one-to-one to the storage blocks, and the logic unit being configured to acquire data in the corresponding storage block and store data to the corresponding storage block.

Abstract: The invention provides a memory device and microelectronic package having the same. The microelectronic package comprises at least one memory device which is adapted to be stacked vertically with one another, and a processing device stacked vertically and adjacently with the at least one memory device and electrically connected to the conductive interconnects. Each of the memory devices comprises a substrate and a plurality of memory units. The substrate presents a front surface and a back surface. The memory units are formed on the front surface, each of which comprises a plurality of memory cells and a plurality of conductive interconnects electrically connected to the memory cells. In each of the memory units, the conductive interconnects contribute to a plurality of signal channels each of which is dedicated to transmit signals from the processing device to one of the memory units and vice versa.

Abstract: The invention provides a memory device and microelectronic package having the same. The microelectronic package comprises at least one memory device which is adapted to be stacked vertically with one another, and a processing device stacked vertically and adjacently with the at least one memory device and electrically connected to the conductive interconnects. Each of the memory devices comprises a substrate and a plurality of memory units. The substrate presents a front surface and a back surface. The memory units are formed on the front surface, each of which comprises a plurality of memory cells and a plurality of conductive interconnects electrically connected to the memory cells. In each of the memory units, the conductive interconnects contribute to a plurality of signal channels each of which is dedicated to transmit signals from the processing device to one of the memory units and vice versa.

Abstract: In one embodiment, a device is described for using ferroelectric material in a memory cell without a selector device. In another embodiment, a method of operating a ferroelectric memory cell without a selector device is described. Other embodiments are likewise described.

Abstract: The present invention provides a smart power supply system including an open storage chamber, a rail, and photovoltaic umbrellas each including a plurality of photovoltaic umbrella panels. The photovoltaic umbrellas may be stored in the storage chamber; the storage chamber is connected to the rail via an opening. When in use, the photovoltaic umbrellas are moved upward from the storage chamber to the rail, then photovoltaic umbrella panels of the photovoltaic umbrellas are expanded. During storage, the photovoltaic umbrella panels of the photovoltaic umbrellas are collapsed, then the photovoltaic umbrellas move downwards along the rail and are then stored in the storage chamber. In the present invention, when use of the photovoltaic umbrellas is required, the photovoltaic umbrellas are expanded outdoor; under certain circumstances such as raining and typhoon, the photovoltaic umbrellas are stored indoor to prevent damages caused to the photovoltaic umbrellas.

Abstract: In one embodiment, a device is described for using ferroelectric material in a memory cell without a selector device. In another embodiment, a method of operating a ferroelectric memory cell without a selector device is described. Other embodiments are likewise described.

Abstract: It is provided a multi-stator rotating electrical machine including: an inner stator; an outer stator; a rotor provided radially between inner stator and the outer stator; an inner gap distance between the rotor and the inner stator; and an outer gap distance between the rotor and the outer stator. An average of the inner gap distance is between 75 and 80 percent of an average of the outer gap distance.

Abstract: In one embodiment, a device is described for using ferroelectric material in a memory cell. In another embodiment, a method of operating a ferroelectric memory cell is described. Other embodiments are likewise described.

Abstract: In one embodiment, a device is described for using ferroelectric material in a memory cell. In another embodiment, a method of operating a ferroelectric memory cell is described. Other embodiments are likewise described.

Abstract: A semiconductor memory device is provided such as a random-access memory (DRAM) including a plurality of DRAM memory cells. Each of the DRAM cells includes an N-type transistor, a P-type transistor, and a common capacitor. The components are disposed in the same direction as the bit-line, with the common capacitor occupying the center region between the N- and P-type transistors. The common capacitor is a metal insulator metal (MIM) capacitor configured by connecting three capacitor elements in parallel. The three capacitors include a first capacitor element formed on a first source/drain region of the N-type transistor, a second capacitor element formed on a first source/drain region of the P-type transistor, and a third element over the field isolation region between the transistors. A bottom electrode of each of these capacitor elements connects the first source/drain region of the N-type transistor to a first source/drain region of the P-type transistor.

Abstract: Embodiments of the invention improve efficiency and address the stability issues that arise when a boost converter is used for both backlight WLEDs and camera flash applications, which require increased voltage or output voltage less than input voltage. In prior solutions, boost converters may suffer poor efficiency when operating in a fixed high output voltage mode or may lose stability by not properly regulating their output when operating in a step-down voltage mode. To improve efficiency of the boost converter, the present invention uses a 100%-pass mode topology when the battery voltage is high enough to support the diode voltage required for the backlight WLEDs or the camera flash. On the other hand, when the battery voltage drops below the required voltage, then the converter switches automatically to boost mode to generate a sufficient output voltage to drive the diodes to the required current level.

Abstract: In one embodiment, a device is described for using ferroelectric material in a memory cell. In another embodiment, a method of operating a ferroelectric memory cell is described. Other embodiments are likewise described.

Abstract: A method of detecting a concentration of a target component by using a reference wavelength includes: defining a wavelength at which a light intensity is insensitive to the variation of the target component concentration as a reference wavelength for the target component; detecting spectra at both the reference wavelength and a further measuring wavelength; processing the spectrum detected at the further measuring wavelength, with the spectrum detected at the reference wavelength as an inner reference, to obtain a characteristic spectrum including specific information of the target component; building a calibration model between the characteristic spectrum and the concentration of the target component; and determining the concentration of the target component based on the calibration model.