Abstract: Implementations disclosed herein may relate to a memory cell, such as a DRAM memory cell, for example.

Abstract: A switching regulator generally includes an output circuit, a comparator, an on-time timer and an error amplifier. The output circuit receives an input voltage and produces an output voltage. The comparator causes the output circuit to turn on the output voltage when a feedback voltage falls below a first reference voltage. The on-time timer causes the output circuit to turn off the output voltage after a time-out period. The error amplifier receives the feedback voltage and a second reference voltage and produces the first reference voltage.

Abstract: A method of detecting a concentration of a target component by using a reference wavelength comprises: defining a wavelength at which a light intensity is insensitive to the variation of the target component concentration as a reference wavelength for the target component; detecting spectra at both the reference wavelength and a further measuring wavelength; processing the spectrum detected at the further measuring wavelength, with the spectrum detected at the reference wavelength as an inner reference, to obtain a characteristic spectrum including specific information of the target component; building a calibration model between the characteristic spectrum and the concentration of the target component; and determining the concentration of the target component based on the calibration model.

Abstract: Various apparatuses, methods and systems for protecting a driver from electrostatic discharge are disclosed herein. For example, some exemplary embodiments provide a driver, including a buffer, a leakage path blocking transistor connected to an output of the buffer, and an output driver connected to an output of the leakage path blocking transistor. Current from the output driver to the buffer is substantially blocked by the leakage path blocking transistor.

Abstract: A solar wireless audio system is provided. The solar wireless audio system includes a transmitting portion and a solar outdoor speaker. The transmitting portion includes a transmitting circuit and an audio input device connected with an input of the transmitting circuit. A receiving circuit and a power amplifier are inside the solar outdoor speaker, and the power amplifier is connected with output of the receiving circuit. Audio input device is a connecting interface for iPod player. Audio detection circuit and power management circuit are inside the solar outdoor speaker. Input of audio detection circuit is connected with output of receiving circuit. Output of audio detection circuit is connected with the inputs of power management circuit and power amplifier, respectively. Output of the power management circuit is connected with power control terminal of power amplifier. The solar outdoor speaker can be switched between sleep mode and active mode.

Abstract: Various apparatuses, methods and systems for protecting a driver from electrostatic discharge are disclosed herein. For example, some exemplary embodiments provide a driver, including a buffer, a leakage path blocking transistor connected to an output of the buffer, and an output driver connected to an output of the leakage path blocking transistor. Current from the output driver to the buffer is substantially blocked by the leakage path blocking transistor.

Abstract: An EPG contents collection and recommendation system includes an EPG database of identifications of available programs. A program information acquisition module applies text classification to detailed descriptions of the available programs. An EPG recommendation module recommends an available program to a user based on the text classification. Preferably, EPG contents are collected from publicly available TV websites and parsed into a uniform format. For example, contents are vectorized, and a Maximum Entropy technique is applied. Also, user interaction with the EPG database is used to form a user profile database. Further, classifiers are trained based on contents of the user profile database, and these classifiers are used to recommend EPG contents to the user.

Abstract: An EPG contents collection and recommendation system includes an EPG database of identifications of available programs. A program information acquisition module applies text classification to detailed descriptions of the available programs. An EPG recommendation module recommends an available program to a user based on the text classification. Preferably, EPG contents are collected from publicly available TV websites and parsed into a uniform format. For example, contents are vectorized, and a Maximum Entropy technique is applied. Also, user interaction with the EPG database is used to form a user profile database. Further, classifiers are trained based on contents of the user profile database, and these classifiers are used to recommend EPG contents to the user.

Abstract: A method for bi-directional data synchronization between different clock frequencies is described wherein a state machine counter is provided a first clock signal having a first frequency. The state machine counter is then provided a second clock signal having a second frequency that is an integer multiple of the first clock frequency. The state machine counter has an integer number of states equivalent to the ratio of the second clock signal frequency to the first clock signal frequency. The first clock signal is applied to reset the state machine counter to an initial state. The state machine counter generates an intermediate clock signal whenever the state machine increments through all states to return to the initial state. The intermediate clock is then applied to synchronize data between the first clock frequency and the second clock frequency.

Abstract: A temperature independent CMOS reference voltage circuit includes a CMOS current mirror circuit containing first and second CMOS transistors of a first polarity. A temperature compensation circuit is coupled to the CMOS current mirror circuit, and contains a first resistor, a second resistor, and third and fourth CMOS transistors of a second polarity. The third and fourth CMOS transistors are configured to operate substantially in a subthreshold region. One of the third and fourth CMOS transistors is diode connected.

Abstract: A fuse-based cell. The fuse-based cell includes a fuse with a programming device electrically coupled to the fuse to program the fuse. A sensing device is electrically coupled to the fuse to sense a programming state of the fuse. A clamping device is electrically coupled to the sensing device to control voltages across the sensing device during programming. A pass device is electrically coupled to the sensing device to control voltages across the sensing device during sensing.

Abstract: A temperature independent CMOS reference voltage circuit includes a CMOS current mirror circuit containing first and second CMOS transistors of a first polarity. A temperature compensation circuit is coupled to the CMOS current mirror circuit, and contains a first resistor, a second resistor, and third and fourth CMOS transistors of a second polarity. The third and fourth CMOS transistors are configured to operate substantially in a subthreshold region. One of the third and fourth CMOS transistors is diode connected.

Abstract: Improved semiconductor integrated circuit random access memory (RAM) features pin-compatible replacement of SRAM devices, while providing low power and high density characteristics of DRAM devices. The refresh operations of a DRAM array are hidden so as to faithfully emulate an SRAM-type interface. The new refresh strategy is based on prohibiting the start of a refresh operation during certain periods but otherwise continuously refreshing the array, rather than affirmatively scheduling refresh at certain times as in the prior art. Short refresh operations are initiated frequently, driven by an internal clock that generates periodic refresh requests, except when a read or write operation is actually accessing the memory array. By isolating the DRAM memory array from I/O structures, external memory accesses are essentially interleaved with refresh operations, rather than temporally segregating them as in prior art.

Abstract: A bias generator circuit with improved phase margin without RC compensation includes: a first transistor MP4; a second transistor MP3 coupled in parallel with the first transistor MP4; an amplifier A1 having a first input coupled to the first and second transistors MP4 and MP3, and to a gate of the second transistor MP3, and a second input coupled to a control voltage node VCTRL; a third transistor MN4 coupled in series with the first transistor MP4; a fourth transistor MN2 coupled in series with the third transistor MN4 and having a gate coupled to an output of the amplifier A1; a fifth transistor MP1; a sixth transistor MP2 coupled in parallel with the fifth transistor MP1; a seventh transistor MN3 coupled in series with the fifth transistor MP1; and an eighth transistor MN1 coupled in series with the seventh transistor MN3 and having a gate coupled to a gate of the fourth transistor MN2.

Abstract: A bias generator circuit with improved phase margin without RC compensation includes: a first transistor MP4; a second transistor MP3 coupled in parallel with the first transistor MP4; an amplifier A1 having a first input coupled to the first and second transistors MP4 and MP3, and to a gate of the second transistor MP3, and a second input coupled to a control voltage node VCTRL; a third transistor MN4 coupled in series with the first transistor MP4; a fourth transistor MN2 coupled in series with the third transistor MN4 and having a gate coupled to an output of the amplifier A1; a fifth transistor MP1; a sixth transistor MP2 coupled in parallel with the fifth transistor MP1; a seventh transistor MN3 coupled in series with the fifth transistor MP1; and an eighth transistor MN1 coupled in series with the seventh transistor MN3 and having a gate coupled to a gate of the fourth transistor MN2.

Abstract: Improved semiconductor integrated circuit random access memory (RAM) features pin-compatible replacement of SRAM devices, while providing low power and high density characteristics of DRAM devices. The refresh operations of a DRAM array are hidden so as to faithfully emulate an SRAM-type interface. The new refresh strategy is based on prohibiting the start of a refresh operation during certain periods but otherwise continuously refreshing the array, rather than affirmatively scheduling refresh at certain times as in the prior art. Short refresh operations are initiated frequently, driven by an internal clock that generates periodic refresh requests, except when a read or write operation is actually accessing the memory array. By isolating the DRAM memory array from I/O structures, external memory accesses are essentially interleaved with refresh operations, rather than temporally segregating them as in prior art.

Abstract: A fuse-based cell. The fuse-based cell includes a fuse with a programming device electrically coupled to the fuse to program the fuse. A sensing device is electrically coupled to the fuse to sense a programming state of the fuse. A clamping device is electrically coupled to the sensing device to control voltages across the sensing device during programming. A pass device is electrically coupled to the sensing device to control voltages across the sensing device during sensing.

Abstract: An oxide anti-fuse structure is provided with vertical-drain NMOS transistors and vertical-source-drain NMOS transistors to obtain higher area density and low programming current requirement.