Abstract: A circuit assembly includes an integrated circuit (IC) die and a first capacitor die. The IC die provides an IC and includes a plurality of first conductive pads. The first capacitor die provides a plurality of capacitors, and includes a plurality of second conductive pads at the first side and a plurality of conductive vias at the second side. At least one of the second conductive pads electrically connects to the capacitors. The conductive vias is adapted to form a plurality of external signal connections of the IC die and the first capacitor die. The IC die is stacked with the first capacitor die in such a way that the first conductive pads electrically connect to the second conductive pads, and surfaces of the IC die and the first capacitor die attaching to each other are substantially of the same size.

Abstract: A memory device includes a memory die, a non-volatile memory circuit, and a logic die. The memory die includes a firs memory space and a second memory space. The non-volatile memory circuit stores a repair table file corresponding to the first memory space. The logic die is coupled to the memory die and the non-volatile memory. The logic die selectively accesses the first memory space or the second memory space of the memory die according a comparing result of an input address and the repair table file. The memory die and is different from the logic die.

Abstract: An interface of a memory circuit includes a chip enable terminal, at least one data terminal, and a data strobe terminal. The chip enable terminal receives a chip enable signal that varies between a first high voltage and a low voltage for enabling the memory circuit. The at least one data terminal receives at least one first data signal that varies between a second high voltage and the low voltage. The data strobe terminal receives a first data strobe signal that periodically varies between the second high voltage and the low voltage. The first data strobe signal is synchronized with the at least one first data signal, and is arranged to latch and sample the at least one first data signal. The first high voltage is higher than the second high voltage, and the second high voltage is higher than the low voltage.

Abstract: A display controller includes a first chip and a second chip. The first chip is configured to control a display device. The second chip is externally coupled to the first chip, and configured to be a random access memory and. The first chip is further configured to provide a first supply power to the second chip and to access the second chip during the controlling of the display device.

Abstract: A method of operating a microelectronic package includes a processing device stacking vertically with at least one memory device. The method includes a step of: reading data stored in a plurality of memory cells of a plurality of memory units of the memory device, with the processing device, with a plurality of signal channels each of which is dedicated to transmit signals from the processing device to one of the memory units and vice versa.

Abstract: A method of assembling a microelectronic package includes the step of: stacking a processing device vertically with at least one memory device and electrically connecting the processing device to a plurality of conductive interconnects of one of the at least one memory device, wherein each of the at least one memory device includes: a substrate, presenting a front surface and a back surface; and a plurality of memory units formed on the front surface, each of which comprises a plurality of memory cells and the conductive interconnects electrically connected to the memory cells; and arranging the conductive interconnects to contribute to a plurality of signal channels each of which dedicated to transmit signals from the processing device to one of the memory units and vice versa.

Abstract: A DRAM chiplet structure is provided. The DRAM chiplet structure includes a first hybrid bonding structure, a DRAM interface structure, and a first DRAM core structure. The first hybrid bonding structure has a first surface and a second surface. The DRAM interface structure is in contact with the first surface of the first hybrid bonding structure. The first DRAM core structure is in contact with the second surface of the first hybrid bonding structure.

Abstract: An interposer structure is provided. The interposer structure includes a plurality of interposer units in an array arrangement from a top view perspective. Each of the interposer units includes a first region and a plurality of second regions. The first region has a capacitor structure. Each of the plurality of second regions is free of the capacitor structure. The first region surrounds the plurality of second regions. A method for manufacturing an interposer structure is also provided.

Abstract: It is provided a multi-stator rotating electrical machine including: an inner stator; an outer stator; a rotor provided radially between inner stator and the outer stator; an inner gap distance between the rotor and the inner stator; and an outer gap distance between the rotor and the outer stator. An average of the inner gap distance is between 75 and 80 percent of an average of the outer gap distance.

Abstract: A method for manufacturing a semiconductor structures is provided. The method includes forming a first hybrid bonding layer over a first wafer having a logic structure, forming a second hybrid bonding layer over a second wafer having a first capacitor structure, bonding the first wafer and the second wafer through a hybrid bonding operation to connect the first hybrid bonding layer and the second hybrid bonding layer, thereby obtaining a first bonded wafer, and the first capacitor structure is electrically connected to the logic structure through the first hybrid bonding layer and the second hybrid bonding layer, and singulating the first bonded wafer to obtain a plurality of semiconductor structures.

Abstract: This disclosure relates to a multiphase converter design with multi-path phase management circuit and output logic. The phase management circuit and output logic can be employed to implement phase adding and shedding operations based on input and output current information and based on control signals for a power stage of the converter. In some examples, the design employs an estimate of an average output current based on a current at an input of the converter for phase control. In additional examples, the design employs cycle-by-cycle current limit and maximum duty-cycle signals to enable phase quickly during load transient. In further examples, the design employs low input and output-current sensed signals for efficient phase shedding and power saving. The design herein improves an overall accuracy of phase adding and shedding, load transient response performance, an operational efficiency and thermal performance of multiphase converter.

Abstract: A capacitor device includes: a substrate; an insulation film, disposed on the substrate; at least one capacitor unit cell, being covered by the insulation film on the substrate, the at least one capacitor unit cell having at least one first electrode and at least one second electrode disposed over the first electrode; an exposed conductive layer, disposed on the at least one capacitor unit cell and the insulation film, the exposed conductive layer having a first conductive pad formed on a first side of the exposed conductive layer and a second conductive pad formed on a second side different from the first side; wherein the first conductive pad and the second conductive pad are electrically connected to the at least one first electrodes and the at least one second electrodes of the at least one capacitor unit cell respectively.

Abstract: In one embodiment, a device is described for using ferroelectric material in a memory cell. In another embodiment, a method of operating a ferroelectric memory cell is described. Other embodiments are likewise described.

Abstract: A method of assembling a microelectronic package includes the step of: stacking a processing device vertically with at least one memory device and electrically connecting the processing device to a plurality of conductive interconnects of one of the at least one memory device, wherein each of the at least one memory device includes: a substrate, presenting a front surface and a back surface; and a plurality of memory units formed on the front surface, each of which comprises a plurality of memory cells and the conductive interconnects electrically connected to the memory cells; and arranging the conductive interconnects to contribute to a plurality of signal channels each of which dedicated to transmit signals from the processing device to one of the memory units and vice versa.

Abstract: A circuit assembly includes an integrated circuit (IC) die and a first capacitor die. The IC die provides an IC and includes a plurality of first conductive pads. The first capacitor die provides a plurality of capacitors, and includes a plurality of second conductive pads at the first side and a plurality of conductive vias at the second side. At least one of the second conductive pads electrically connects to the capacitors. The conductive vias is adapted to form a plurality of external signal connections of the IC die and the first capacitor die. The IC die is stacked with the first capacitor die in such a way that the first conductive pads electrically connect to the second conductive pads, and surfaces of the IC die and the first capacitor die attaching to each other are substantially of the same size.

Abstract: A method for manufacturing a semiconductor structures is provided. The method includes forming a first hybrid bonding layer over a first wafer having a logic structure, forming a second hybrid bonding layer over a second wafer having a first capacitor structure, bonding the first wafer and the second wafer through a hybrid bonding operation to connect the first hybrid bonding layer and the second hybrid bonding layer, thereby obtaining a first bonded wafer, and the first capacitor structure is electrically connected to the logic structure through the first hybrid bonding layer and the second hybrid bonding layer, and singulating the first bonded wafer to obtain a plurality of semiconductor structures.

Abstract: This disclosure relates to a multiphase converter design with multi-path phase management circuit and output logic. The phase management circuit and output logic can be employed to implement phase adding and shedding operations based on input and output current information and based on control signals for a power stage of the converter. In some examples, the design employs an estimate of an average output current based on a current at an input of the converter for phase control. In additional examples, the design employs cycle-by-cycle current limit and maximum duty-cycle signals to enable phase quickly during load transient. In further examples, the design employs low input and output-current sensed signals for efficient phase shedding and power saving. The design herein improves an overall accuracy of phase adding and shedding, load transient response performance, an operational efficiency and thermal performance of multiphase converter.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a first hybrid bonding structure, a memory structure, and a control circuit structure. The first hybrid bonding layer includes a first surface and a second surface. The memory structure is in contact with the first surface. The control circuit structure is configured to control the memory structure. The control circuit structure is in contact with the second surface. A system in package (SiP) structure and a method for manufacturing a plurality of semiconductor structures are also provided.

Abstract: The present disclosure relates to a neural network artificial intelligence chip and a method for forming the same. The neural network artificial intelligence chip includes: a storage circuit, that includes a plurality of storage blocks; and a calculation circuit, that includes a plurality of logic units, the logic units being correspondingly coupled one-to-one to the storage blocks, and the logic unit being configured to acquire data in the corresponding storage block and store data to the corresponding storage block.

Abstract: The invention provides a memory device and microelectronic package having the same. The microelectronic package comprises at least one memory device which is adapted to be stacked vertically with one another, and a processing device stacked vertically and adjacently with the at least one memory device and electrically connected to the conductive interconnects. Each of the memory devices comprises a substrate and a plurality of memory units. The substrate presents a front surface and a back surface. The memory units are formed on the front surface, each of which comprises a plurality of memory cells and a plurality of conductive interconnects electrically connected to the memory cells. In each of the memory units, the conductive interconnects contribute to a plurality of signal channels each of which is dedicated to transmit signals from the processing device to one of the memory units and vice versa.