Patents by Inventor Wen Lin

Wen Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200186763
    Abstract: A projection device includes a light source module, an optical engine module, a projection lens, a housing, and at least one first heat dissipating element. The housing comprises a first end and a second end opposite to each other. The at least one first heat dissipating element is disposed in the housing, and each of the at least one first heat dissipating element includes a first plate portion, a second plate portion, and a first fin portion. The first plate portion is connected to the light source module. The second plate portion is connected to the first plate portion. The first fin portion is connected to the second plate portion and includes a plurality of first fins arranged at intervals. These first fins are arranged between the first end and the second end.
    Type: Application
    Filed: December 5, 2019
    Publication date: June 11, 2020
    Inventors: JHIH-HAO CHEN, WEI-MIN CHIEN, TSUNG-CHING LIN, SHI-WEN LIN
  • Publication number: 20200183563
    Abstract: A display panel able to receive full fingerprint impressions in a display area together with command touches, in addition to showing images, includes a substrate, scan lines, data lines, touch scan lines, touch lines, sub-pixels, and fingerprint sensing units. A method for driving such multifunctional touch display panel is also provided.
    Type: Application
    Filed: September 12, 2019
    Publication date: June 11, 2020
    Inventors: YU-FU WENG, CHIEN-WEN LIN, CHIA-LIN LIU
  • Publication number: 20200183263
    Abstract: A projection device includes: a light source module for generating an illumination beam; an optical engine module disposed on a transmission path of the illumination beam for forming an image beam; a projection lens disposed on a transmission path of the image beam for projecting the image beam to an outside of the projection device; and a housing having opposite bottom and top portions, and a side wall connected between and surrounding the portions and having an air inflow region adjacent to the bottom portion and an air exhaust region adjacent to the top portion. The light source module, the optical engine module and the projection lens are disposed in the housing adjacent to the top portion, wherein the image beam is projected to the outside toward the bottom portion. The projection device of the invention can effectively dissipate heat.
    Type: Application
    Filed: December 5, 2019
    Publication date: June 11, 2020
    Inventors: WEI-MIN CHIEN, JHIH-HAO CHEN, TSUNG-CHING LIN, SHI-WEN LIN
  • Patent number: 10679357
    Abstract: An image-based object tracking system including a photographic device and a computing equipment is provided. The photographic device captures a first image of a scene at a first time and a second image of the scene at a second time subsequent to the first time. The computing equipment determines an area of the scene in the first and second images, which includes a midline of the scene in the first and second images, overlaps the first and second images for determining whether a distance between a first object in the first image and a second object in the second image is less than a predetermined threshold in response to the first object being in the area and the second object not being in the area, and updates an entry object count or an exit object count in response to the distance being less than the predetermined threshold.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: June 9, 2020
    Assignee: QUANTA COMPUTER INC.
    Inventors: Chen-Chung Lee, Chia-Hung Lin, Ming-Jen Chen, Ching-Wen Lin, Wei-Lun Tsai, Jui-Sen Tuan, You-Dian Lin
  • Publication number: 20200168721
    Abstract: A complementary metal-oxide-semiconductor (CMOS) semiconductor device includes a substrate. The CMOS semiconductor device further includes an isolation region in the substrate. The CMOS semiconductor device further includes a P-metal gate electrode extending over the isolation region, wherein the P-metal gate electrode includes a first function metal and a TiN layer doped with a first material. The CMOS semiconductor device further includes an N-metal gate electrode extending over the isolation region, wherein the N-metal gate electrode includes a second function metal and a TiN layer doped with a second material different from the first material, a portion of the P-metal gate electrode is between a portion of the N-metal gate electrode and the substrate, and a portion of the TiN layer doped with the second material is between the portion of the P-metal gate electrode and the substrate.
    Type: Application
    Filed: January 31, 2020
    Publication date: May 28, 2020
    Inventors: Ming ZHU, Hui-Wen LIN, Harry Hak-Lay CHUANG, Bao-Ru YOUNG, Yuan-Sheng HUANG, Ryan Chia-Jen CHEN, Chao-Cheng CHEN, Kuo-Cheng CHING, Ting-Hua HSIEH, Carlos H. DIAZ
  • Patent number: 10665509
    Abstract: A method for manufacturing chip package includes the steps below. A wafer having an upper surface and a lower surface opposite thereto is provided, in which conductive bumps are disposed on the upper surface. The upper surface of the wafer is diced to form trenches. A first insulation layer exposing the conductive bumps is formed on the upper surface and in the trenches. A surface treatment layer is formed on the conductive bumps, and a top surface of the surface treatment layer is higher than that of the first insulation layer. The wafer is thinned from the lower surface toward the upper surface to expose the first insulation layer in the trenches. A second insulation layer is formed below the lower surface. The first and second insulation layers are diced along a center of each trench to form chip packages.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: May 26, 2020
    Assignee: COMCHIP TECHNOLOGY CO., LTD.
    Inventors: Chien-Chih Lai, Hung-Wen Lin
  • Patent number: 10666500
    Abstract: Techniques are described for avoiding traffic black-holing in a multi-homed Ethernet virtual private networks (EVPNs) in which a customer device (CE) is multi-homed to a plurality of multi-homing provider edge devices (PEs) via respective links of an Ethernet segment. An overlay network is created over the Ethernet segment, and the multi-homing PEs of the EVPN are configured with a common anycast IP address for respective virtual network interfaces. Upon election as active designated forwarder (DF) for the EVPN, the DF PE of the multi-homing PEs advertises toward the customer network an IGP metric for the anycast IP address that is lower than the IGP metric(s) advertised by any of the non-DF standby PE routers segment to direct the CE to forward network packets from the customer network to the DF PE over the respective link of the Ethernet segment.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: May 26, 2020
    Assignee: Juniper Networks, Inc.
    Inventors: Tapraj Singh, Wen Lin, SelvaKumar Sivaraj, Rukesh Dorai, Sunesh Rustagi
  • Publication number: 20200161183
    Abstract: A method of manufacturing chip package is disclosed. The method includes providing a wafer having a first surface and a second surface, in which the wafer includes conductive bumps disposed on the first surface; thinning the wafer from the second surface toward the first surface; dicing the wafer to form chips, in which each chip has a third surface and a fourth surface, and at least one of the conductive bumps is disposed on the third surface; disposing the chips on a substrate, such that the conductive bumps are disposed between the substrate and the third surface, in which any two adjacent of the chips are spaced apart by a gap ranging from 50 ?m to 140 ?m; forming an insulating layer filling the gaps and covering the chips; and dicing the insulating layer along each gap to form a plurality of chip packages.
    Type: Application
    Filed: May 6, 2019
    Publication date: May 21, 2020
    Inventors: Chien-Chih LAI, Hung-Wen LIN
  • Publication number: 20200161412
    Abstract: An electronic device includes a flexible substrate and a conductive wire. The flexible substrate includes a first bending region and a side region connected to the first bending region. The conductive wire is disposed on the flexible substrate and includes a metal portion and a plurality of openings disposed in the metal portion. A ratio of a total width of the metal portion disposed in the first bending region to a total width of the metal portion disposed in the side region is in a range from 0.8 to 1.2, and a length of one of the openings in the first bending region is less than or equal to a length of one of the openings in the side region.
    Type: Application
    Filed: October 17, 2019
    Publication date: May 21, 2020
    Inventors: Ya-Wen Lin, Chien-Chih Chen, Yen-Hsi Tu, Cheng-Wei Chang, Shu-Hui Yang
  • Publication number: 20200161182
    Abstract: A method for manufacturing chip package is disclosed. The method includes providing a wafer having conductive bumps disposed on a first surface; forming a first adhesion layer and a first carrier board; thinning the wafer; forming a first insulating layer; forming a second adhesion layer and a second carrier board; heating the first adhesion layer to a first temperature to remove the first carrier board and the first adhesion layer; forming trenches; forming a third adhesion layer and a third carrier board; heating the second adhesion layer to a second temperature to remove the second carrier board and the second adhesion layer; forming a second insulating layer filing the trenches; heating the third adhesion layer to a third temperature to remove the third carrier board and the third adhesion layer; and dicing the first insulating layer and the second insulating layer along each trench.
    Type: Application
    Filed: May 6, 2019
    Publication date: May 21, 2020
    Inventors: Chien-Chih LAI, Hung-Wen LIN
  • Patent number: 10656744
    Abstract: A thin film transistor array substrate in a touch display panel having reinforced common voltage uniformity on sub-electrodes therein includes a common electrode layer, a driving circuit, a controlling switch, a plurality of first lines, at least one second line, and at least one third line. The common electrode layer includes the spaced sub-electrodes. Each sub-electrode uses a first line electrically connect to the driving circuit and the controlling switch. The at least one second line is electrically connected to the driving circuit and the controlling switch, and when the controlling switch is turned on, the second line is electrically connected to the first lines, the driving circuit thus applying a common voltage to the sub-electrodes. A touch display panel using the thin film transistor array substrate is also provided.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: May 19, 2020
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Yu-Fu Weng, Chien-Wen Lin, Chia-Lin Liu, Tzu-Yu Cheng
  • Patent number: 10656525
    Abstract: A photoresist baking apparatus is provided. The photoresist baking apparatus comprises a baking chamber including an inlet, an outlet and a cover sealed connected thereon. The cover is applied to guide the hot air entering the baking chamber and includes a heating device for maintaining the temperature of the hot air. The heating device is disposed on the cover for heating the hot air flowing to the cover and maintaining the temperature of the hot air to be consistent when the hot air flowing to the outlet, thereby to prevent from the photoresist volatile condensing and dripping due to decreased temperature after the photoresist volatile contacting the cover and affecting the product quality, and to guarantee the temperature homogeneity inside the baking chamber.
    Type: Grant
    Filed: July 2, 2018
    Date of Patent: May 19, 2020
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Chung-jen Chen, Ming-wen Lin, Yan-ze Li, Chilin Wu, Zhikun Wu
  • Patent number: 10658263
    Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first semiconductor die, a second semiconductor die, a molding compound, a heat dissipation module and an adhesive material. The first and second semiconductor dies are different types of dies and are disposed side by side. The molding compound encloses the first and second semiconductor dies. The heat dissipation module is located directly on and in contact with the back sides of the first and second semiconductor dies. The adhesive material is filled and contacted between the heat dissipation module and the molding compound. The semiconductor package has a central region and a peripheral region surrounding the central region. The first and second semiconductor dies are located within the central region. A sidewall of the heat dissipation module, a sidewall of the adhesive material and a sidewall of the molding compound are substantially coplanar.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: May 19, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chi-Yang Yu, Chin-Liang Chen, Kuan-Lin Ho, Yu-Min Liang, Wen-Lin Chen
  • Publication number: 20200152546
    Abstract: Examples described herein provide for an electronic device apparatus with multiple thermally conductive paths for heat dissipation. In an example, an electronic device apparatus includes a package comprising a die attached to a package substrate. The electronic device apparatus further includes a ring stiffener disposed around the die and on the package substrate, a heat sink disposed on the package, and a wedge disposed between the heat sink and the ring stiffener.
    Type: Application
    Filed: November 9, 2018
    Publication date: May 14, 2020
    Applicant: Xilinx, Inc.
    Inventors: Gamal Refai-Ahmed, Ho Hyung Lee, Hui-Wen Lin, Henley Liu, Suresh Ramalingam
  • Publication number: 20200150523
    Abstract: An extreme ultraviolet (EUV) mask is received. The EUV mask has an EUV pellicle disposed thereover. The EUV pellicle is coupled to the EUV mask at least in part via glue that is disposed on the EUV mask. The EUV pellicle is removed, thereby exposing the glue. A localized glue-removal process is performed by targeting a region of the EUV mask on which the glue is disposed. The localized glue-removal process is performed without affecting other regions of the EUV mask that do not have the glue disposed thereon. The localized glue-removal process may include injecting a cleaning chemical onto the glue and removing a waste chemical produced by the cleaning chemical and the glue. The localized glue-removal process may also include a plasma process that applies plasma to the glue. The localized glue-removal process may further include a laser process that shoots a focused laser beam at the glue.
    Type: Application
    Filed: December 27, 2019
    Publication date: May 14, 2020
    Inventors: Tzu-Ting Chou, Chung-Hsuan Liu, Kuan-Wen Lin, Chi-Lun Lu, Ting-Hao Hsu, Sheng-Chi Chin
  • Patent number: 10644987
    Abstract: A provider edge (PE) device may determine a first identifier, corresponding to a first connection for a first service, and a second identifier, corresponding to a second connection for a second service, where the first connection is between a first customer edge (CE) device and the PE device, and the second connection is between a second CE device and the PE device. The PE device may advertise a first route, associated with the first service, based on the first identifier and a label corresponding to a network instance. The PE device may advertise a second route, associated with the second service, based on the second identifier and the label. The PE device may determine that the first connection is unavailable, and withdraw advertisement of the first route, while maintaining advertisement of the second route, to indicate, to a remote PE device, that the first connection is unavailable.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: May 5, 2020
    Assignee: Juniper Networks, Inc.
    Inventors: Wen Lin, John E. Drake
  • Patent number: 10641285
    Abstract: A fan includes an impeller, a drive device, and a frame structure. The driving device drives the impeller to rotate, and the frame structure accommodates the driving device. The frame structure includes a frame body, a first frame, a second frame, a base and a plurality of supports. The frame body has first engaging portions and second engaging portions, which are disposed annularly at the upper end and the lower end of the frame body, respectively. The first frame is mounted on the frame body and disposed corresponding to the first engaging portions. The second frame is mounted on the frame body and disposed corresponding to the second engaging portions. The base is disposed within the frame body and located adjacent to the second frame. The supports are disposed around the base. The material of the frame body is different from that of the first and second frames.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: May 5, 2020
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Tai-Ying Tu, Yi-Wen Lin, Chih-Hui Wu, Ming-Kai Hsieh
  • Patent number: 10642395
    Abstract: A shift register driving a touch display device generates shifted pulse signals shifted by a specified phase. The shift register includes unit circuits connected in multiple stages. Each unit circuit includes an output terminal, an input transistor, an output transistor, and a pull-up transistor. The input transistor is controlled by a first control signal and outputs a high-level voltage to a first node based on the value of a trigger signal. The output transistor outputs the shifted pulse signal, which is synchronous with a clock control signal, based on the value of the high-level voltage of the first node. A blank period is inserted between the Nth unit circuit and the (N+1)th unit circuit. After the blank period, the pull-up transistor clamps the voltage of the output terminal of the (N+1)th unit circuit at a high-level voltage.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: May 5, 2020
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Yu-Fu Weng, Chien-Wen Lin, Tzu-Yu Cheng
  • Publication number: 20200133348
    Abstract: A control method is provided. The control method is applied to an electronic device. The control method includes the following steps: detecting a virtual screen signal; allocating a virtual screen image buffer module for temporarily storing virtual screen image information according to the virtual screen signal; integrating the virtual screen image information and second screen image information into an integrated image data stream by a direct mode; outputting a first screen image data stream to a first screen of an electronic device, so that the first screen displays a first image according to the first screen image data stream; and outputting the integrated image data stream to a second screen of the electronic device, so that the second screen displays a second image according to the integrated image data stream.
    Type: Application
    Filed: April 9, 2019
    Publication date: April 30, 2020
    Inventors: Che-Min Lin, Chin-Wen Lin
  • Publication number: 20200129498
    Abstract: Described herein are compounds and compositions for treating glaucoma and/or reducing intraocular pressure. Compositions may comprise an isoquinoline compound and a prostaglandin or a prostaglandin analog. Compounds described herein include those in which an isoquinoline compound is covalently linked to a prostaglandin or a prostaglandin analog, and those in which an isoquinoline compound and a prostaglandin free acid together form a salt.
    Type: Application
    Filed: December 30, 2019
    Publication date: April 30, 2020
    Inventors: Casey Kopczynski, Cheng-Wen Lin, Jill Marie Sturdivant, Mitchell A. deLong