Abstract: A protein analysis platform includes a platform body comprising: a gel working unit provided in a top portion of the platform body and comprising a gel accommodation area for accommodating at least one gel; at least one electrophoresis tank provided along a side of the gel accommodation area and provided with at least one electrode; and a blotting layer stack provided in a bottom portion of the gel working unit and comprising an electrode layer; wherein a removable bottom plate is provided between the gel working unit and the blotting layer stack and detachably corresponds to a bottom side of the gel accommodation area. The protein analysis platform is used for western blotting or next-generation western blotting, wherein the protein analysis platform can quickly complete steps such as gel casting, electrophoresis, and blotting in one platform.

Abstract: In some embodiments, a computer-implemented method includes ascertaining a multitier topology representation of an edge cloud network; generating a pseudo node topology representation of the edge cloud network from the multitier topology representation; and utilizing the pseudo node topology representation of the edge cloud network to ascertain minimum-latency pseudo-node-based edge cloud clusters (ECCs), the minimum-latency pseudo-node-based ECCs being utilized to minimize a latency of user requests routed through the edge cloud network from a user of the edge cloud network. In some embodiments of the computer-implemented method, the minimum-latency pseudo-node-based ECCs are ascertained based upon a pseudo-node-based round-trip-times (RTTs) assessment from the user of the edge cloud network, the user requests being routed to the minimum-latency pseudo-node-based ECCs ascertained using the pseudo node topology representation.

Abstract: Metal oxide films are reduced to metal with an atmospheric pressure argon and hydrogen plasma at temperatures between 25 and 250° C. A 40-nm-thick copper oxide layer on a copper-coated silicon wafer, 300 mm in diameter, can be fully removed by the argon and hydrogen plasma in under two minutes at 150° C. The fast rate of metal oxide reduction to metal demonstrates that this process is well suited for front- and back-end semiconductor manufacturing, such as for example, flux-free flip chip bonding of microbumps.

Abstract: The disclosure provides a display module, including a display substrate and a FPC board; the display substrate includes a first base substrate, first bonding terminals, first impedance-test bonding terminals, and an antenna radiation structure; the FPC board includes a second base substrate, second bonding terminals, second impedance-test bonding terminals, and an antenna receiving structure; the first bonding terminals are bonded and connected to the second bonding terminals; the first impedance-test bonding terminals are bonded and connected to the second impedance-test bonding terminals; the antenna radiation structure has two ends respectively connected to two first impedance-test bonding terminals; the antenna receiving structure has two ends respectively connected to two second impedance-test bonding terminals; and the two first impedance-test bonding terminals connected to the antenna radiation structure are respectively bonded and connected to the two second impedance-test bonding terminals connected

Abstract: An optical film includes a grid layer having a first surface, a second surface, light-shading portions, and light-transmitting portions. The light-shading portions and the light-transmitting portions are located between the first surface and the second surface, and the light-shading portions and the light-transmitting portions are alternately arranged along the first surface. Each light-shading portion has a third surface, a fourth surface, a fifth surface, a sixth surface, and a seventh surface. An angle between the fourth and third surfaces is A1, an angle between the fifth and third surfaces is A2, an angle between the sixth and second surfaces is A3, and an angle between the seventh and second surfaces is A4. Wherein 85°<A1?90°, 85°<A2?90°, 0°<A3<85°, 0°<A4<85°, A2?A4, and A1?A3. A display device is also provided.

Abstract: Disclosed are a lithium aluminum hydrotalcite-based solid electrolyte film, a preparation method and use thereof, and a lithium battery including the same. The lithium aluminum hydrotalcite-based solid electrolyte film includes: a solid electrolyte film substrate formed by an organic polymer, and a lithium salt and a lithium aluminum hydrotalcite uniformly dispersed in the solid electrolyte film substrate, wherein the lithium aluminum hydrotalcite has a content of 50 wt % to 80 wt %, based on a total mass of the solid electrolyte film substrate after removal of the lithium salt; and the organic polymer includes one or more selected from the group consisting of polyethylene glycol diacrylate, polyethylene oxide, polypropylene carbonate, and polyvinylidene fluoride-hexafluoropropylene copolymer.

Abstract: The present disclosure is related to STING agonists, linker-payloads thereof, and conjugates thereof, pharmaceutical compositions thereof, and the use of the agonists, conjugates, and pharmaceutical compositions to induce a STING-mediated immune response and/or for the treatment of diseases and disorders mediated by STING.

Abstract: A package-on-package (PoP) structure includes a first package structure and a second package structure stacked on the first package structure. The first package structure includes a die, conductive structures, an encapsulant, and a conductive pattern layer. The conductive structures surround the die. The encapsulant laterally encapsulates the die and the conductive structures. The conductive pattern layer is disposed over and in physical contact with a top surface of the encapsulant and top surfaces of the conductive structures. An entire bottom surface of the conductive pattern layer is located at a same level height, and an entirety of the top surface of the encapsulant and an entirety of the top surfaces of the conductive structures are located at the same level height.

Abstract: A method of fabricating a memory device at least includes the following steps. A first stack structure is formed above a substrate. The first stack structure includes a plurality of first insulating layers and a plurality of first conductive layers alternately stacked. A top layer of the first stack structure includes a plurality of anti-oxidation atoms therein. A second stack structure is formed on the first stack structure. The second stack structure includes a plurality of second insulating layers and a plurality of middle layers alternately stacked. A slit trench is formed to extend from the second stack structure to a top first conductor layer of the plurality of first conductor layers. A protective layer is formed on a sidewall of the top first conductive layer exposed by the slit trench. The memory device may be a 3D NAND flash memory with high capacity and high performance.

Abstract: A semiconductor module includes a substrate, at least one chip, at least one signal assembly, a first molding compound, and a second molding compound. The chip is disposed on the substrate and electrically connected to the substrate. The signal assembly is disposed on the substrate in a normal direction of the substrate and electrically connected to the substrate. The first molding compound is disposed on the substrate. The first molding compound at least covers the chip and has at least one opening, and the opening exposes the signal assembly. The second molding compound is disposed on the substrate and fills the opening. The second molding compound is located between the signal assembly and the first molding compound, and covers the signal assembly. At least one contact interface is formed between the second molding compound and the first molding compound.

Abstract: A memory device includes, from bottom to top, a substrate, a laminated layer and a stacked structure. Vertical channel pillars penetrate through the stacked structure and the laminated layer. First isolation structures are disposed aside the vertical channel pillars and penetrate through a lower part of the stacked structure. Second isolation structures are disposed over the first isolation structures and penetrate through an upper part of the stacked structure. Common source lines are disposed aside the vertical channel pillars and penetrate through the stacked structure and part of the laminated layer. From a top view, the common source lines extend in a first direction. Each of the first and second isolation structures has, in the first direction, two wide end portions respectively adjacent to two common source lines. The memory device may be applied in the process of manufacturing a 3D NAND flash memory with high capacity and high performance.

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a wafer, powering redistribution layers, and grounding redistribution layers. The powering redistribution layers are disposed on the wafer. The grounding redistribution layers are disposed on the wafer, in which each of the powering redistribution layers and a corresponding one of the grounding redistributions layers form a capacitor.

Abstract: A package substrate is provided, in which a thinner second dielectric layer is formed on one side of a circuit structure including a first dielectric layer, so as to prevent large stress difference between two opposite sides of the circuit structure, thereby preventing the package substrate from warpage problems. A method of fabricating the package substrate is also provided.

Abstract: The disclosure provides a display module, including a display substrate and a FPC board; the display substrate includes a first base substrate, first bonding terminals, first impedance-test bonding terminals, and an antenna radiation structure; the FPC board includes a second base substrate, second bonding terminals, second impedance-test bonding terminals, and an antenna receiving structure; the first bonding terminals are bonded and connected to the second bonding terminals; the first impedance-test bonding terminals are bonded and connected to the second impedance-test bonding terminals; the antenna radiation structure has two ends respectively connected to two first impedance-test bonding terminals; the antenna receiving structure has two ends respectively connected to two second impedance-test bonding terminals; and the two first impedance-test bonding terminals connected to the antenna radiation structure are respectively bonded and connected to the two second impedance-test bonding terminals connected

Abstract: A display may include an array of pixels such as light-emitting diode pixels. The pixels may include multiple circuitry decks that each include one or more circuit components such as transistors, capacitors, and/or resistors. The circuitry decks may be vertically stacked. Each circuitry deck may include a planarization layer formed from a siloxane material that conforms to underlying components and provides a planar upper surface. In this way, circuitry components may be vertically stacked to mitigate the size of each pixel footprint. The circuitry components may include capacitors that include both a high-k dielectric layer and a low-k dielectric layer. The display pixel may include a via with a width of less than 1 micron.

Abstract: An electronic device includes a first graphics processing subsystem, a second graphics processing subsystem, and a screen. The first graphics processing subsystem includes a first application processor, a first graphics processing unit, and a first memory. The second graphics processing subsystem includes a second application processor, a second graphics processing unit, and a second memory. The first graphics processing unit renders a first GUI. The screen displays the first GUI. The second graphics processing unit renders a second GUI, and the second GUI and the first GUI belong to different interface types. The screen displays the second GUI. A display processing method applied to the electronic device is also provided, wherein the first graphics processing subsystem can be switched to the second graphics processing subsystem based on complexity of a to-be-displayed GUI.

Abstract: A semiconductor device includes a substrate, at least one semiconductor fin, and at least one epitaxy structure. The semiconductor fin is present on the substrate. The semiconductor fin has at least one recess thereon. The epitaxy structure is present in the recess of the semiconductor fin. The epitaxy structure includes a topmost portion, a first portion and a second portion arranged along a direction from the semiconductor fin to the substrate. The first portion has a germanium atomic percentage higher than a germanium atomic percentage of the topmost portion and a germanium atomic percentage of the second portion.

Abstract: A transmission rate management method is provided. The transmission rate management method is applied to a transmission rate management device. The transmission rate management method includes the steps of calculating a total available data traffic of the transmission rate management device based on a data plan for the transmission rate management device, wherein the total available data traffic corresponds to a period of time; allocating to each of one or more client devices currently connected to the transmission rate management device one available data traffic corresponding to the period of time according to the total available data traffic; and adjusting a transmission rate of a client device of the one or more client devices based on a remaining data traffic of the available data traffic of the client device.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a fin active region formed on a semiconductor substrate and spanning between a first sidewall of a first shallow trench isolation (STI) feature and a second sidewall of a second STI feature; an anti-punch through (APT) feature of a first type conductivity; and a channel material layer of the first type conductivity, disposed on the APT feature and having a second doping concentration less than the first doping concentration. The APT feature is formed on the fin active region, spans between the first sidewall and the second sidewall, and has a first doping concentration.

Abstract: A light-emitting component includes a light-emitting unit and an electrically insulating layer. The light-emitting unit includes a first semiconductor layer, an active layer, and a second semiconductor layer, which are stacked on one another along a stacking direction in such order. The second semiconductor has a lower surface distal from the active layer. The electrically insulating layer is disposed to cover a first portion and to expose a second portion of the lower surface of the second semiconductor layer. A fluorine-containing region is formed in the second semiconductor layer. Methods for making the light-emitting component are also disclosed.