Abstract: Provided are a protein containing an amino acid sequence capable of binding to a peptide fragment of a substrate GPRP, a fibrinogen-like protein 1 (FGL1) containing the amino acid sequence, and a fibrinogen domain (FD) of the FGL1, wherein a single FD protein also has a function the same as or similar to that of the FGL1. The FGL1 and FD, which have different action mechanisms from existing drugs, can inhibit fibrin assembly in the process of thrombogenesis by means of competing for fibrin substrate binding pockets. The FGL1 and FD can have a stronger affinity to the substrate by means of mutation, thereby effectively enhancing a usage effect of drugs for treating thrombus.

Abstract: The present disclosure discloses a combined apparatus for experimentation on different storage modes of carbon dioxide, which comprises a displacement device, a storage reaction device and a measuring device, wherein the displacement device comprises a displacement pump, and an intermediate oil-water container and an intermediate carbon dioxide container that are arranged in parallel, the displacement pump is connected to a first end of the parallel connection of the intermediate oil-water container and the intermediate carbon dioxide container, and an inlet end of the storage reaction device is connected to a second end of the parallel connection of the intermediate oil-water container and the intermediate carbon dioxide container; the measuring device comprises a weigher, a first pressure detector, a gas-liquid separator, a gas meter and a mineral analyzer, wherein the first pressure detector is arranged in the intermediate oil-water container, and the gas-liquid separator is connected to the outlet end of

Abstract: A device includes a substrate including a low-resistance top surface and a fin structure including a first fin and a second fin. Each of the first and second fins includes a low-resistance fin-top surface and two low-resistance sidewall surfaces. The device includes an insulation material over the top surface of the substrate and between the first fin and the second fin. The fin-top surface and a first portion of the sidewall surfaces of each of the first and the second fins are above the insulation material. The device further includes a dielectric layer over the insulation material and in direct contact with the fin-top surface and the first portion of the sidewall surfaces of each of the first and the second fins; a first electrode in direct contact with the fin-top surface of the first fin; and a second electrode over the dielectric layer that is over the second fin.

Abstract: A method includes forming a redistribution structure over a carrier, the redistribution structure having conductive features on a surface of the redistribution structure distal the carrier; forming a conductive pillar over the surface of the redistribution structure; attaching a die to the surface of the redistribution structure adjacent to the conductive pillar, where die connectors of the die are electrically coupled to the conductive features of the redistribution structure; and attaching a pre-made substrate to the conductive pillar through a conductive joint, where the conductive joint is on the conductive pillar and comprises a different material from the conductive pillar, where the conductive joint and the conductive pillar electrically couple the redistribution structure to the pre-made substrate.

Abstract: A composite comprises a carbonaceous and a metallic nanotube conjugated with a carbonaceous support. The composite may be used to remove contaminants from water.

Abstract: A device includes a first semiconductor strip, a first gate dielectric encircling the first semiconductor strip, a second semiconductor strip overlapping the first semiconductor strip, and a second gate dielectric encircling the second semiconductor strip. The first gate dielectric contacts the first gate dielectric. A gate electrode has a portion over the second semiconductor strip, and additional portions on opposite sides of the first and the second semiconductor strips and the first and the second gate dielectrics.

Abstract: Systems and methods are provided for fabricating semiconductor device structures on a substrate. A first fin structure is formed on a substrate. A second fin structure is formed on the substrate. A first semiconductor material is formed on both the first fin structure and the second fin structure. A second semiconductor material is formed on the first semiconductor material on both the first fin structure and the second fin structure. The first semiconductor material on the first fin structure is oxidized to form a first oxide. The second semiconductor material on the first fin structure is removed. A first dielectric material and a first electrode are formed on the first fin structure. A second dielectric material and a second electrode are formed on the second fin structure.

Abstract: A display may include an array of pixels. Each pixel in the array includes an organic light-emitting diode coupled to associated semiconducting oxide transistors. The semiconducting oxide transistors may exhibit different device characteristics. Some of the semiconducting oxide transistors may be formed using a first oxide layer formed from a first semiconducting oxide material using first processing steps, whereas other semiconducting oxide transistors are formed using a second oxide layer formed from a second semiconducting oxide material using second processing steps different than the first processing steps. The display may include three or more different semiconducting oxide layers formed during different processing steps.

Abstract: The present disclosure provides a flexible printed circuit board and a display apparatus. The flexible printed circuit board includes a plurality of bonding pins, where the plurality of bonding pins are configured to be bonded with a display panel, and the plurality of bonding pins include impedance test pins; and an antenna coil, including two metal connecting wires and the two impedance test pins, where the metal connecting wires are electrically connected between the impedance test pins and a near field communication module; and when the plurality of bonding pins are bonded with the display panel, the two impedance test pins are electrically connected through a conducting wire in the display panel.

Abstract: Disclosed are an energy conversion module and an energy conversion device. The energy conversion module includes an encapsulation structure and an integrated module packaged therein, the integrated module includes a trace, a power chip, a transistor control element and an energy storage device. The trace includes at least two electrodes, one is exposed from a first surface of the encapsulation structure, and the other is exposed from a second surface of the encapsulation structure. The first surface is opposite to the second surface. The power chip is respectively connected to the two electrodes of the trace. The transistor control element controls the power chip to perform energy conversion through the trace. The energy storage device supplies energy to the transistor control element through the trace.

Abstract: The current disclosure provides a semiconductor fabrication method that defines the height of gate structures at the formation of the gate structure. A gate line-end region is formed by removing a portion of a gate structure. A resulted recess is filled with a dielectric material is chosen to have a material property suitable for a later contact formation process of forming a metal contact. A metal contact structure is formed through the recess filling dielectric layer to connect to a gate structure and/or a source/drain region.

Abstract: A method includes forming a gate stack on a middle portion of s semiconductor fin, and forming a first gate spacer on a sidewall of the gate stack. After the first gate spacer is formed, a template dielectric region is formed to cover the semiconductor fin. The method further includes recessing the template dielectric region. After the recessing, a second gate spacer is formed on the sidewall of the gate stack. The end portion of the semiconductor fin is etched to form a recess in the template dielectric region. A source/drain region is epitaxially grown in the recess.

Abstract: A heat dissipation structure includes a substrate and an annular groove. The substrate has an upper surface and a lower surface opposite to each other. The annular groove is configured on the upper surface of the substrate to divide the substrate into a configuration area and a periphery area. The annular groove is located between the configuration area and the periphery area. A depth of the annular groove is less than or equal to half of a thickness of the substrate.

Abstract: A circuit substrate includes a base material, a first electrode, and a second electrode. The base material has an upper side and a lower side opposite to each other in a length direction. The first electrode extends and is configured on the base material along the length direction. The second electrode is configured beside the first electrode and includes a first portion and a second portion connected to each other. The first portion is configured on the base material along the length direction. The second portion is configured on the base material along a width direction and is located between the upper side and the first electrode. A cross-sectional width of the first portion becomes larger from the lower side to the upper side.

Abstract: A power semiconductor package signal connection component includes a cylinder having a first through hole and two bases respectively disposed on opposite sides of the cylinder. Each base includes a continuous protrusion pattern and has a flat surface, a curved surface, and a second through hole. The flat surface is connected to the curved surface, and a first side of the curved surface is connected to the cylinder. The second through hole runs through the curved surface and communicates with the first through hole. The continuous protrusion pattern is connected to a second side of the curved surface and is located on the flat surface.

Abstract: The present disclosure discloses a combined apparatus for experimentation on different storage modes of carbon dioxide, which comprises a displacement device, a storage reaction device and a measuring device, wherein the displacement device comprises a displacement pump, and an intermediate oil-water container and an intermediate carbon dioxide container that are arranged in parallel, the displacement pump is connected to a first end of the parallel connection of the intermediate oil-water container and the intermediate carbon dioxide container, and an inlet end of the storage reaction device is connected to a second end of the parallel connection of the intermediate oil-water container and the intermediate carbon dioxide container; the measuring device comprises a weigher, a first pressure detector, a gas-liquid separator, a gas meter and a mineral analyzer, wherein the first pressure detector is arranged in the intermediate oil-water container, and the gas-liquid separator is connected to the outlet end of

Abstract: A shuttered keystone jack assembly is provided in the disclosure. The shutter keystone jack assembly includes a jack housing, a frame, a shutter and an elastic member. The frame is detachably disposed on the jack housing and defining a receiving opening. The shutter is pivotally connected to the frame and selectively covering the receiving opening. The elastic member includes a first end portion and a second end portion, and the first end portion and the second end portion respectively abut against the frame and the shutter.

Abstract: A fluorescence image registration method includes obtaining at least one fluorescence image of a biochip. An interior local area is selected. Sums of pixel values in the interior local area along a first direction and a second direction are obtained. A plurality of first template lines is selected to find a minimum total value of the sums of pixel values corresponding to the first template lines. Pixel-level correction is performed on a local area of the track line to obtain pixel-level track cross. Other track crosses on the biochip is obtained, and the pixel-level correction is performed on the other track crosses. The position of the pixel-level track line is corrected by a center-of-gravity method to obtain the subpixel-level position of the track line. The subpixel-level positions of all sites uniformly distributed on the biochip is obtained.

Abstract: A device includes a substrate including a low-resistance top surface and a fin structure including a first fin and a second fin. Each of the first and second fins includes a low-resistance fin-top surface and two low-resistance sidewall surfaces. The device includes an insulation material over the top surface of the substrate and between the first fin and the second fin. The fin-top surface and a first portion of the sidewall surfaces of each of the first and the second fins are above the insulation material. The device further includes a dielectric layer over the insulation material and in direct contact with the fin-top surface and the first portion of the sidewall surfaces of each of the first and the second fins; a first electrode in direct contact with the fin-top surface of the first fin; and a second electrode over the dielectric layer that is over the second fin.

Abstract: A semiconductor structure is provided. The semiconductor structure has a device region and a periphery region adjacent to the device region. The periphery region comprises an array contact defining region and a periphery contact defining region. The semiconductor structure comprises a substrate, a staircase structure, an etch stop layer, a plurality of array contacts, and a plurality of periphery contacts. The staircase structure is disposed on the substrate in the periphery region. The staircase structure comprises conductive layers and dielectric layers disposed alternately. The etch stop layer is disposed on the staircase structure in the array contact defining region. The array contacts are disposed on the staircase structure and through the etch stop layer in the array contact defining region. The periphery contacts are through the staircase structure in the periphery contact defining region.