Patents by Inventor Wen Liu

Wen Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11955554
    Abstract: A method of fabrication of a multi-gate semiconductor device that includes providing a fin having a plurality of a first type of epitaxial layers and a plurality of a second type of epitaxial layers. The plurality of the second type of epitaxial layers is oxidized in the source/drain region. A first portion of a first layer of the second type of epitaxial layers is removed in a channel region of the fin to form an opening between a first layer of the first type of epitaxial layer and a second layer of the first type of epitaxial layer. A portion of a gate structure is then formed in the opening.
    Type: Grant
    Filed: July 15, 2022
    Date of Patent: April 9, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Huan-Sheng Wei, Hung-Li Chiang, Chia-Wen Liu, Yi-Ming Sheu, Zhiqiang Wu, Chung-Cheng Wu, Ying-Keung Leung
  • Patent number: 11955392
    Abstract: One aspect of this description relates to a testing apparatus including an advance process control monitor (APCM) in a first wafer, a plurality of pads disposed over and coupled to the APCM. The plurality of pads are in a second wafer. The testing apparatus includes a testing unit disposed between the first wafer and the second wafer. The testing unit is coupled to the APCM. The testing unit includes a metal structure within a dielectric. The testing apparatus includes a plurality of through silicon vias (TSVs) extending in a first direction from the first wafer, through the dielectric of the testing unit, to the second wafer.
    Type: Grant
    Filed: May 12, 2021
    Date of Patent: April 9, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shuo-Wen Chang, Yu-Hsien Li, Min-Tar Liu, Yuan-Yao Chang
  • Patent number: 11955474
    Abstract: An electrostatic discharge (ESD) protection circuit is provided. The protection circuit includes a MOS transistor and a resistor. The MOS transistor is electrically coupled to a core circuit. The resistor is electrically coupling to a gate of the MOS transistor for creating a bias on the gate to directing an ESD current to a ground when an ESD event occurs on the core circuit. A layout of the MOS transistor is spaced apart from a layout of the core circuit by a layout of a dummy structure. The resistor is formed by utilizing a portion of the dummy structure.
    Type: Grant
    Filed: August 22, 2022
    Date of Patent: April 9, 2024
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Fang-Wen Liu
  • Patent number: 11951587
    Abstract: The present disclosure is directed to techniques of zone-based target control in chemical mechanical polishing of wafers. Multiple zones are identified on a surface of a wafer. The CMP target is achieved on each zone in a sequence of CMP processes. Each CMP process in the sequence achieves the CMP target for only one zone, using a CMP process selective to other zones.
    Type: Grant
    Filed: August 12, 2019
    Date of Patent: April 9, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Che-Liang Chung, Che-Hao Tu, Kei-Wei Chen, Chih-Wen Liu
  • Publication number: 20240112912
    Abstract: A method of manufacturing a semiconductor device includes the following steps. A photoresist layer is formed over a material layer on a substrate. The photoresist layer has a composition including a solvent and a first photo-active compound dissolved in the solvent. The first photo-active compound is represented by the following formula (Al) or formula (A2): Zr12O8(OH)14(RCO2)18??Formula (A1); or Hf6O4(OH)6(RCO2)10??Formula (A2). R in the formula (A1) and R in the formula (A2) each include one of the following formulae (1) to (6): The photoresist layer is patterned. The material layer is etched using the photoresist layer as an etch mask.
    Type: Application
    Filed: July 28, 2023
    Publication date: April 4, 2024
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TSING HUA UNIVERSITY
    Inventors: Jui-Hsiung LIU, Yu-Fang TSENG, Pin-Chia LIAO, Burn Jeng LIN, Tsai-Sheng GAU, Po-Hsiung CHEN, Po-Wen CHIU
  • Publication number: 20240114810
    Abstract: A semiconductor structure includes: an etch-stop dielectric layer overlying a substrate and including a first opening therethrough; a silicon oxide plate overlying the etch-stop dielectric layer and including a second opening therethrough; a first conductive structure including a first electrode and extending through the second opening and the first opening; a memory film contacting a top surface of the first conductive structure and including a material that provides at least two resistive states having different electrical resistivity; and a second conductive structure including a second electrode and contacting a top surface of the memory film.
    Type: Application
    Filed: April 20, 2023
    Publication date: April 4, 2024
    Inventors: Fu-Ting Sung, Jhih-Bin Chen, Hung-Shu Huang, Hong Ming Liu, Hsia-Wei Chen, Yu-Wen Liao, Wen-Ting Chu
  • Publication number: 20240114243
    Abstract: Some implementations of the disclosure relate to an imaging system including one or more image sensors and a Z-stage. The imaging system is configured to perform operations including: capturing, using the one or more image sensors, a first image of a first pair of spots projected at a first sample location of a sample; determining whether or not the first image of the first pair of spots is valid; and when the first image is determined to be valid: obtaining, based on the first image, a current separation distance measurement of the first pair of spots; and controlling, based at least on the current separation distance measurement, the Z-stage to focus the imaging system at the first sample location.
    Type: Application
    Filed: September 25, 2023
    Publication date: April 4, 2024
    Inventors: Yu Chen, Gregory Holst, John Earney, Patrick Wen, Chia-Hsi Liu, Daeyong Sim
  • Publication number: 20240108230
    Abstract: The embodiments of the disclosure provide a method for evaluating a health condition indicator of a subject, a host, and a computer readable storage medium. The method includes: obtaining a reference heart rate of the subject and determining a heart rate indicator of the subject according to the reference heart rate; determining a fitness indicator of the subject based on physiological information of the subject; determining an age indicator of the subject based on an age of the subject; and determining the health condition indicator of the subject at least based on the heart rate indicator, the fitness indicator, and the age indicator.
    Type: Application
    Filed: September 30, 2022
    Publication date: April 4, 2024
    Applicant: BOMDIC INC.
    Inventors: Yao Shiao, Shao Wen Tou, Yu-Ting Liu, Amy Pei-Ling Chiu
  • Publication number: 20240111210
    Abstract: A method of manufacturing a semiconductor device includes the following steps. A photoresist layer is formed over a material layer on a substrate. The photoresist layer has a composition including a solvent and a first photo-active compound dissolved in the solvent. The first photo-active compound is represented by the following formula (A1) or formula (A2): Zr12O8(OH)14(RCO2)18 ??Formula (A1); or Hf6O4(OH)6(RCO2)10 ??Formula (A2). R in the formula (A1) and R in the formula (A2) each include one of the following formulae (1) to (6): The photoresist layer is patterned. The material layer is etched using the photoresist layer as an etch mask.
    Type: Application
    Filed: May 9, 2023
    Publication date: April 4, 2024
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TSING HUA UNIVERSITY
    Inventors: Jui-Hsiung LIU, Pin-Chia LIAO, Ting-An LIN, Ting-An SHIH, Yu-Fang TSENG, Burn Jeng LIN, Tsai-Sheng GAU, Po-Hsiung CHEN, Po-Wen CHIU
  • Publication number: 20240109063
    Abstract: An apparatus includes a flow cell, an imaging assembly, and a processor. The flow cell includes a channel and a plurality of reaction sites. The imaging assembly is operable to receive light emitted from the reaction sites in response to an excitation light. The processor is configured to drive relative movement between at least a portion of the imaging assembly and the flow cell along a continuous range of motion to thereby enable the imaging assembly to capture images along the length of the channel. The processor is also configured to activate the imaging assembly to capture one or more calibration images of one or more calibration regions of the channel, during a first portion of the continuous range of motion. The processor is also configured to activate the imaging assembly to capture images of the reaction sites during a second portion of the continuous range of motion.
    Type: Application
    Filed: September 28, 2023
    Publication date: April 4, 2024
    Inventors: Dustin BLAIR, Patrick WEN, John EARNEY, Anmiv PRABHU, Rachel ABASKHARON, Gregory HOLST, Chia-Hsi LIU, Ravi THAKUR, Dakota WATSON, Kevin BARTIG, Daeyong SIM
  • Patent number: 11948336
    Abstract: Aspects of the disclosure provide methods and apparatuses for point cloud compression and decompression. In some examples, an apparatus for point cloud compression/decompression includes processing circuitry. In some examples, the processing circuitry receives a bitstream carrying compressed data for a point cloud. The processing circuitry determines that a current node in an octree structure is eligible for an isolated mode. The octree structure corresponds to three dimensional (3D) partitions of a space of the point cloud. Then the processing circuitry determines, based on information of one or more other nodes, a single isolated point flag for the current node that indicates whether the current node is coded with a single isolated point.
    Type: Grant
    Filed: June 22, 2021
    Date of Patent: April 2, 2024
    Assignee: TENCENT AMERICA LLC
    Inventors: Xiang Zhang, Wen Gao, Shan Liu
  • Publication number: 20240105659
    Abstract: A method of manufacturing a semiconductor device is provided. The method includes forming a redistribution layer (RDL) over a semiconductor die. A portion of the RDL contacts a die pad of the semiconductor die. A metal layer is formed on a top surface and sidewalls of the RDL and configured to encase the RDL. A non-conductive layer is formed over the metal layer and underlying RDL. An opening in the non-conductive layer is formed exposing a portion of the metal layer formed on the RDL. An under-bump metallization (UBM) is formed in the opening and conductively connected to the die pad by way of the metal layer and RDL.
    Type: Application
    Filed: September 28, 2022
    Publication date: March 28, 2024
    Inventors: Kuan-Hsiang Mao, Yufu Liu, Wen Hung Huang, Tsung Nan Lo
  • Patent number: 11941856
    Abstract: A method, computer program, and computer system is provided for decoding point cloud data. Data corresponding to a point cloud is received. A number of contexts associated with the received data is reduced based on reducing a size of an array corresponding to syntax elements for predictive tree-based coding of the point cloud. The data corresponding to the point cloud is decoded based on the reduced number of contexts.
    Type: Grant
    Filed: May 19, 2021
    Date of Patent: March 26, 2024
    Assignee: TENCENT AMERICA LLC
    Inventors: Wen Gao, Xiang Zhang, Shan Liu
  • Patent number: 11943221
    Abstract: Aspects of the invention include systems and methods configured to prevent masquerading service attacks. A non-limiting example computer-implemented method includes sending, from a first server in a cloud environment, a communication request comprising an application programming interface (API) key and a first server identifier to an identity and access management (IAM) server of the cloud environment. The API key can be uniquely assigned by the IAM server to a first component of the first server. The first server receives a credential that includes a token for the first component and sends the credential to a second server. The second server sends the credential, a second server identifier, and an identifier for a second component of the second server to the IAM server. The second server receives an acknowledgment from the IAM server and sends the acknowledgment to the first server.
    Type: Grant
    Filed: August 25, 2021
    Date of Patent: March 26, 2024
    Assignee: International Business Machines Corporation
    Inventors: Sen Wang, Mei Liu, Si Bo Niu, Wen Yi Gao, Zong Xiong Z X Wang, Guoxiang Zhang, Xiao Yi Tian, Xian Wei Zhang
  • Publication number: 20240091758
    Abstract: The invention concerns a sonocatalyst which is suitable for promoting a chemical reaction initiated by ultrasound irradiation. The invention also relates to a method of catalysing a reaction by exposing the sonocatalyst to ultrasound. The invention also relates to the use of a sonocatalyst as described herein in a method as described herein.
    Type: Application
    Filed: December 6, 2021
    Publication date: March 21, 2024
    Inventors: James KWAN, Qianwenhao FAN, Xiaoqian SU, Paul Wen LIU, Umesh Sai JONNALAGADDA, Lakshmi Deepika BHARATULA
  • Publication number: 20240091170
    Abstract: Provided are catechol nanoparticles, catechol protein nanoparticles, and a preparation method and use thereof. The method includes: adding a tannin compound-containing natural herb medicine into water to obtain a mixture, and subjecting the mixture to heating reflux extraction to obtain a herb medicine extract and subjecting the herb medicine extract to fractionation to obtain the catechol nanoparticles.
    Type: Application
    Filed: August 1, 2023
    Publication date: March 21, 2024
    Applicant: Shihezi University
    Inventors: Bo HAN, Jingmin Fan, Hang Yu, Rui Xue, Jiawei Guan, Yu Xu, Linyun He, Ji Liu, Chengyu Jiang, Xin Lu, Xiangze Kong, Wei Yu, Wen Chen
  • Publication number: 20240097376
    Abstract: Compact electrical connectors with improved water resistance. A connector may have an outer shell and an inner shell disposed in the outer shell. A lead assembly may be partially disposed in the inner shell. A mating end of one of the outer shell and inner shell may extend beyond a mating end of the other shell, defining a corner. A seal may be disposed in the corner, such that the seal is mechanically supported when the connector is pressed, in a mating direction, against a mating component, blocking ingress of environmental contaminants. The seal may also block any opening between the mating end of the outer and inner shells. The seal is made from a curable material such that it may readily fill such an opening. The connector may also have a body seal in the lead assembly.
    Type: Application
    Filed: September 15, 2023
    Publication date: March 21, 2024
    Applicant: Amphenol East Asia Electronic Technology (Shenzhen) Co., Ltd.
    Inventors: Hui Wen Liu, Zhimin Qin
  • Publication number: 20240094343
    Abstract: A method, device, system, and storage medium for tracking a moving target are provided. The method uses three-dimensional radar observation data to construct a state vector and a motion model of the moving target, thereby to construct a state equation and an observation equation for achieving filtering and tracking within a linear Gaussian framework. The disclosure is also suitable for a moving target in a two-dimensional scene with a distance and an azimuth, and the disclosure use a two-dimensional observation vector to construct a dynamic system to achieving tracking of the moving target. The disclosure can be used in radar systems containing Doppler measurements, and tracking of moving targets can be implemented by performing dimension-expansion processing on observation equations.
    Type: Application
    Filed: August 16, 2023
    Publication date: March 21, 2024
    Inventors: XuanZhi Zhao, Wen Zhang, ZengLi Liu, Kang Liu, HaiYan Quan, Yi Peng, JingMin Tang, YaoLian Song, Zheng Chen
  • Patent number: 11935753
    Abstract: A method for forming a packaged integrated circuit device includes providing a semiconductor wafer having a plurality of integrated circuit devices, each integrated circuit device extending into the semiconductor wafer to a first depth, and grinding a backside of the silicon wafer to no more than the first depth. The method further includes forming a backside cut between the integrated circuit devices. The backside cut extends to within the first depth, but the backside cut does not extend completely through the semiconductor wafer. The backside cut exposes a plurality of edges of each of the integrated circuit devices. The method further includes depositing, on the backside of the wafer, a metallization layer on a bottom surface of the integrated circuit devices and on the edges.
    Type: Grant
    Filed: December 9, 2021
    Date of Patent: March 19, 2024
    Assignee: NXP B.V
    Inventors: Kuan-Hsiang Mao, Wen Hung Huang, Che Ming Fang, Yufu Liu
  • Patent number: 11935722
    Abstract: This disclosure is directed to solutions of detecting and classifying wafer defects using machine learning techniques. The solutions take only one coarse resolution digital microscope image of a target wafer, and use machine learning techniques to process the coarse SEM image to review and classify a defect on the target wafer. Because only one coarse SEM image of the wafer is needed, the defect review and classification throughput and efficiency are improved. Further, the techniques are not distractive and may be integrated with other defect detecting and classification techniques.
    Type: Grant
    Filed: July 21, 2022
    Date of Patent: March 19, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung-Pin Chou, Sheng-Wen Huang, Jun-Xiu Liu