Abstract: A vision-based enhanced omni-directional defect detection method is provided. The method includes: performing posture adjustment on equipment, changing an equipment angle and a transmission speed, acquiring a multi-angle detection picture, and performing information fusion and classification. By means of the method, the influence of natural and human factors is solved, the problem of missing detection is solved by adoption of defect feature enhancement, and the part detection accuracy is improved.

Abstract: A composite cathode preparation method is provided. The composite cathode preparation method includes steps of: (a) providing a cathode material, a solid electrolyte, a conductive carbon, and an alcohol solvent, wherein the cathode material includes a plurality of first particles and has a composition of Li[NiaCobMncAld]O2, a+b+c+d=1, 0.8<a?1, 0?b<1, 0?c<1, and 0?d<1, wherein the solid electrolyte has a composition of Li3InClxFy, x+y?6, 0?x?6, and 0?y?3; (b) mixing the cathode material, the solid electrolyte, the conductive carbon, and the alcohol solvent to form a first slurry; (c) mixing the first slurry and a binder to form a second slurry; and (d) subjecting the second slurry to a heat treatment and remove the alcohol solvent to form the composite cathode, wherein the composite cathode includes a plurality of second particles, each of the second particles includes one of the plurality of first particles and the solid electrolyte coated on the first particles.

Abstract: An integrated fan-out package includes a first redistribution structure, a die, a plurality of conductive structures, an encapsulant, and a second redistribution structure. The die is bonded to the first redistribution structure through flip-chip bonding. The conductive structures surround the die. The encapsulant encapsulates the die and the conductive structures. The second redistribution structure is disposed on the encapsulant and is electrically connected to the first redistribution structure through the conductive structures. The second redistribution structure includes at least one conductive pattern layer that is in physical contact with the encapsulant. Top surfaces of the conductive structures contacting the second redistribution structure are coplanar with a top surface of the encapsulant.

Abstract: A semiconductor device assembly includes a first remote distribution layer (RDL), the first RDL comprising a lower outermost planar surface of the semiconductor device assembly; a first semiconductor die directly coupled to an upper surface of the first RDL by a first plurality of interconnects; a second RDL, the second RDL comprising an upper outermost planar surface of the semiconductor device assembly opposite the lower outermost planar surface; a second semiconductor die directly coupled to a lower surface of the second RDL by a second plurality of interconnects; an encapsulant material disposed between the first RDL and the second RDL and at least partially encapsulating the first and second semiconductor dies; and a third plurality of interconnects extending fully between and directly coupling the upper surface of the first RDL and the lower surface of the second RDL.

Abstract: Disclosed are a lithium aluminum hydrotalcite-based solid electrolyte film, a preparation method and use thereof, and a lithium battery including the same. The lithium aluminum hydrotalcite-based solid electrolyte film includes: a solid electrolyte film substrate formed by an organic polymer, and a lithium salt and a lithium aluminum hydrotalcite uniformly dispersed in the solid electrolyte film substrate, wherein the lithium aluminum hydrotalcite has a content of 50 wt % to 80 wt %, based on a total mass of the solid electrolyte film substrate after removal of the lithium salt; and the organic polymer includes one or more selected from the group consisting of polyethylene glycol diacrylate, polyethylene oxide, polypropylene carbonate, and polyvinylidene fluoride-hexafluoropropylene copolymer.

Abstract: An optical film includes a grid layer having a first surface, a second surface, light-shading portions, and light-transmitting portions. The light-shading portions and the light-transmitting portions are located between the first surface and the second surface, and the light-shading portions and the light-transmitting portions are alternately arranged along the first surface. Each light-shading portion has a third surface, a fourth surface, a fifth surface, a sixth surface, and a seventh surface. An angle between the fourth and third surfaces is A1, an angle between the fifth and third surfaces is A2, an angle between the sixth and second surfaces is A3, and an angle between the seventh and second surfaces is A4. Wherein 85°<A1?90°, 85°<A2?90°, 0°<A3<85°, 0°<A4<85°, A2?A4, and A1?A3. A display device is also provided.

Abstract: Disclosed herein is a method of determining subject sensitivity to a WEE1 inhibitor, comprising obtaining or having obtained a biological sample from the subject, and performing or having performed at least one assay on the biological sample to determine if the subject has an altered function of CCNE1. Also disclosed are methods of treating cancer with a WEE1 inhibitor, comprising identifying a subject having (a) the cancer and (b) endogenous or altered function of CCNE1; and administering an effective amount of the WEE1 inhibitor, or a pharmaceutically acceptable salt thereof, to the subject.

Abstract: A cathode material including a plurality of particles. Each of the plurality of particles includes a core layer and a coating layer coated thereon. The core layer includes a lithium metal oxide material having a composition of Li[NiaCobMncAld]O2, wherein a+b+c+d=1, 0<a<1, 0<b<1, 0?c<1, and 0?d<1. The coating layer includes a solid electrolyte formed by a reaction of a first material on the core layer. The solid electrolyte has a composition of Li3InClxFy, wherein x+y=6, 0<x<6, and 0<y<6. The lithium metal oxide material, the first material, and a solvent are mixed to form a precursor, and the precursor is heat-treated to form the cathode material. The first material includes lithium, indium, chlorine, and fluorine. The lithium metal oxide material and the solid electrolyte have a weight ratio ranged from 1:0.3 to 1:0.6.

Abstract: A backlight module includes a light guide plate, a light source, an optical film, and first and second prism sheets. The light source and the optical film are respectively located on a light incident surface and a light exit surface of the light guide plate. The optical film includes a substrate and optical microstructures including first and second inclined surfaces and having an extending direction parallel to the light incident surface. There are respectively first and second base angles between the first and second inclined surfaces and a surface of the substrate. An angle range of the first and second base angles is 50 to 70 degrees. The first and second prism sheets t each have prism structures. An angle range of an included angle between extending directions of the optical microstructures and the prism structures is 85 to 95 degrees. A display device having the backlight module is proposed.

Abstract: A flexible printed circuit board includes a substrate, a first conductive layer, a first protective layer and a support body. The substrate has a device region and a non-device region, and the device region is configured to be coupled to a chip. The first conductive layer is located on a side of the substrate. The first protective layer is located on a side of the first conductive layer away from the substrate. The first protective layer is provided therein with an accommodation space. The support body is located at least in the accommodation space. An orthographic projection of the support body on the substrate at least overlaps with at least one of the device region and the non-device region of the substrate.

Abstract: The semiconductor device includes a substrate, a stack disposed on the substrate, a first common source line and a second common source line disposed in the stack and connected to the substrate. The stack includes insulating layers and conductive layers alternately arranged. The first common source line and the second common source line are extended along a first direction and are arranged in a second direction that is perpendicular to the first direction. The first common source line includes a first segment and a second segment spaced apart by a first common source line cut. The second common source line includes a third segment and a fourth segment spaced apart by a second common source line cut. The first common source line cut is shifted relative to the second common source line cut in the first direction. A method of forming the semiconductor device is also disclosed.

Abstract: A manufacturing method of a package-on-package structure includes forming a first package structure and staking a second package structure over the first package structure. The first package structure is formed by at least the following steps. A first redistribution structure is provided. Conductive structures are formed on the first redistribution structure. A die is placed between the conductive structures. The die and the conductive structures are encapsulated by an encapsulant. The encapsulant is planarized such that an entirety of a top surface of the encapsulant is coplanar with an entirety of top surfaces of the conductive structures. A second redistribution structure is formed on the encapsulant. The second redistribution structure includes a conductive pattern layer that is in physical contact with the top surfaces of the encapsulant and the conductive structures. An entire bottom surface of the conductive pattern layer is located at a same level height.

Abstract: Methods for improving joinder between a surface-mount package and a printed circuit board are disclosed. The warpage at a corner of the surface-mount package and at a corresponding corner of a joint area on the printed circuit board are measured to determine the degree of mismatch. A mini-pad is applied to the corner between the surface-mount package and the joint area on the printed circuit board. The thickness of the mini-pad pushes against the surface-mount package and the printed circuit board, reducing the degree of mismatch below a critical dimension of a ball grid array of the surface-mount package. The surface-mount package can then be soldered to the joint area, reducing or preventing the formation of solder bridges and short circuits.

Abstract: A backlight module, including a light guide element, a light source, and first and second optical elements, is provided. The first optical element is disposed on a side of a light exit surface of the light guide element. The first optical element includes first prism structures, each including a first base angle and a second base angle away from the light incident surface relative to the first base angle. The first base angle is different from the second base angle. The second optical element is disposed on a side of the light exit surface. The first optical element is located between the light guide element and the second optical element. The second optical element includes second prism structures, each including a third base angle and a fourth base angle away from the light incident surface relative to the third base angle. A display device is also provided.

Abstract: A semiconductor device includes a semiconductor die. The semiconductor die includes a device layer, an interconnect layer over the device layer, a conductive pad over the interconnect layer, a conductive seed layer directly on the conductive pad, and a passivation layer encapsulating the conductive pad and the conductive seed layer. The conductive pad is between the interconnect layer and the conductive seed layer.

Abstract: A semiconductor device includes a FinFET component, a plurality of patterned dummy semiconductor fins arranged aside a plurality of fins of the FinFET component, an isolation structure formed on the patterned dummy semiconductor fins, and a tuning component formed on the patterned dummy semiconductor fins and electrically connected to the FinFET component. A height of the patterned dummy semiconductor fins is shorter than that of the fins of the FinFET component.

Abstract: Various embodiments of the present application are directed towards an ion-sensitive field-effect transistor for enhanced sensitivity. In some embodiments, a substrate comprises a pair of first source/drain regions and a pair of second source/drain regions. Further, a first gate electrode and a second gate electrode underlie the substrate. The first gate electrode is laterally between the first source/drain regions, and the second gate electrode is laterally between the second source/drain regions. An interconnect structure underlies the substrate and defines conductive paths electrically shorting the second source/drain regions and the second gate electrode together. A passivation layer is over the substrate and defines a first well and a second well. The first and second wells respectively overlie the first and second gate electrodes, and a sensing layer lines the substrate in the first and second wells. In some embodiments, sensing probes are in the first well, but not the second well.

Abstract: A process tool including a polishing pad on a top surface of a wafer platen. A wafer carrier is configured to hold a wafer over the polishing pad. A slurry dispenser is configured to dispense an abrasive slurry including a plurality of charged abrasive particles having a first polarity onto the polishing pad. A first conductive rod is within the wafer platen and coupled to a first voltage supply. A wafer roller is configured to support the wafer. A first wafer brush is arranged beside the wafer roller. A second conductive rod is within the first wafer brush and coupled to a second voltage supply. The first voltage supply is configured to apply a first charge having a second polarity, opposite the first polarity, to the first conductive rod. The second voltage supply is configured to apply a second charge having the second polarity to the second conductive rod.

Abstract: A method comprising: providing a slurry to a polishing pad that is disposed on a wafer platen, the slurry comprising a plurality of electrically charged abrasive particles having a first electrical polarity; moving a first side of a wafer into contact with the slurry and the polishing pad; applying a first electrical charge having a second electrical polarity, opposite the first electrical polarity, to a first conductive rod; moving the first side of the wafer away from the polishing pad while the first electrical charge is applied to the first conductive rod; moving a first wafer brush into contact with the first side of the wafer; applying a second electrical charge having the second electrical polarity, opposite the first electrical polarity, to a second conductive rod arranged within the first wafer brush; and moving the first wafer brush away from the first side of the wafer.