Patents by Inventor Wen Liu

Wen Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Radiotracer precursor for imaging of hypoxic tissue, radiotracer, and method for preparing the same
    Patent number: 9044519
    Abstract: A radiotracer precursor for imaging of hypoxic tissues, a radiotracer and a method for preparing the same are revealed. The radiotracer precursor, DANI, includes a nitroimidazole functional group with a feature of retention in hypoxic tissues and a bifunctional ligand able to complex with radioisotopes. Thus DANI can be used to produce radiotracers stayed in hypoxic tissues and the radiotracers are applied to medical imaging of malignant tumor with hypoxic layer.
    Type: Grant
    Filed: June 18, 2013
    Date of Patent: June 2, 2015
    Assignee: Atomic Energy Council—Institute of Nuclear Energy Research
    Inventors: Show-Wen Liu, Yu Chang, Cheng-Fang Hsu, Tsung-Hsien Chiang, Sheng-Lun Lin, Chih-Yuan Lin
  • Fin Structure of Semiconductor Device
    Publication number: 20150144998
    Abstract: A fin structure of a semiconductor device, such as a fin field effect transistor (FinFET), and a method of manufacture, is provided. In an embodiment, trenches are formed in a substrate, and a liner is formed along sidewalls of the trenches, wherein a region between adjacent trenches define a fin. A dielectric material is formed in the trenches. Portions of the semiconductor material of the fin are replaced with a second semiconductor material and a third semiconductor material, the second semiconductor material having a different lattice constant than the substrate and the third semiconductor material having a different lattice constant than the second semiconductor material. Portions of the second semiconductor material are oxidized.
    Type: Application
    Filed: November 26, 2013
    Publication date: May 28, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Ching, Jiun-Jia Huang, Chao-Hsiung Wang, Chi-Wen Liu
  • SELECTIVE FIN-SHAPING PROCESS
    Publication number: 20150132911
    Abstract: A method of forming a fin field-effect transistor (FinFET) includes forming a plurality of fins on a substrate. The method further includes forming an oxide layer on the substrate, wherein a bottom portion of each fin of the plurality of fins is embedded in the oxide layer, and the bottom portion of each fin of the plurality of fins has substantially a same shape. The method further includes shaping at least one fin of the plurality of fins, wherein a top portion of the at least one fin has a different shape from a top portion of another fin of the plurality of fins.
    Type: Application
    Filed: January 16, 2015
    Publication date: May 14, 2015
    Inventors: Clement Hsingjen WANN, Ling-Yen YEH, Chi-Yuan SHIH, Yi-Tang LIN, Chih-Sheng CHANG, Chi-Wen LIU
  • MECHANISMS FOR SEMICONDUCTOR DEVICE STRUCTURE
    Publication number: 20150123175
    Abstract: Embodiments of mechanisms of a semiconductor device structure are provided. The semiconductor device structure includes a substrate and a metal gate structure formed over the substrate. The semiconductor device structure further includes a funnel shaped hard mask structure formed over the metal gate structure. In addition, a method for forming the semiconductor device structure is also provided.
    Type: Application
    Filed: November 6, 2013
    Publication date: May 7, 2015
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsin-Ying LIN, Mei-Yun WANG, Hsien-Cheng WANG, Fu-Kai YANG, Shih-Wen LIU, Audrey Hsiao-Chiu HSU
  • INTEGRATED CIRCUIT STRUCTURE WITH THINNED CONTACT
    Publication number: 20150123213
    Abstract: Embodiments of mechanism for an integrated circuit (IC) structure are provided. The IC structure includes a substrate including a first diffusion region, a second diffusion region, and an isolation structure separating the first diffusion region and the second diffusion region. The IC structure further includes a gate structure formed over the substrate, and the gate structure extends from the first diffusion region to the second diffusion region. The IC structure further includes a contact formed over the substrate, and the contact includes a wide portion over the first diffusion region and the second diffusion region and a thin portion over the isolation structure.
    Type: Application
    Filed: November 6, 2013
    Publication date: May 7, 2015
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Hsin-Ying LIN, Mei-Yun WANG, Hsien-Cheng WANG, Shih-Wen LIU, Fu-Kai YANG, Audrey Hsiao-Chiu HSU
  • Radiotracer precursor BANI for imaging of hypoxic tissue, radiotracer, and method for preparing the same
    Patent number: 9024035
    Abstract: The present invention relates to a radiotracer precursor for imaging of hypoxic tissues, a radiotracer and a method for preparing the same. The radiotracer precursor, BANI, includes a nitroimidazole functional group with a feature of retention in hypoxic tissues and a bifunctional ligand able to complex with radioisotopes. Thus BANI can be used to produce radiotracers retained in hypoxic tissues and the radiotracers are applied to medical imaging of malignant tumor with hypoxic layer.
    Type: Grant
    Filed: July 22, 2013
    Date of Patent: May 5, 2015
    Assignee: Atomic Energy Council—Institute of Nuclear Energy Research
    Inventors: Show-Wen Liu, Yu Chang, Cheng-Fang Hsu, Sheng-Lun Lin, Tsung-Hsien Chiang, Chih-Yuan Lin
  • Motor with rotor positioning component
    Patent number: 9024497
    Abstract: A motor includes a base, a rotor unit and a driving unit. The base has opposite first and second surfaces. The rotor unit includes a magnet unit disposed on a rotatable magnet carrier to face the first surface of the base. The driving unit includes a circuit board disposed between the base and the magnet unit, induction coils disposed on the circuit board and operatively associated with the magnet unit, a sensor unit disposed on the circuit board and spaced apart from the induction coils, and a rotor positioning component disposed on the second surface of the base and capable of magnet attraction with the magnet unit for positioning the rotor unit relative to the sensor unit when the rotor unit stops rotating.
    Type: Grant
    Filed: January 25, 2013
    Date of Patent: May 5, 2015
    Assignee: Yen Sun Technology Corp.
    Inventors: Chien-Jung Chen, Hsien-Wen Liu, Chih-Tsung Hsu, Tzu-Wen Tsai
  • Motor with rotor positioning component
    Patent number: 9024506
    Abstract: A motor includes a base, a rotor unit and a driving unit. The base has opposite first and second surfaces. The rotor unit includes a magnet unit disposed on a rotatable magnet carrier to face the first surface of the base. The driving unit includes induction coils disposed on a circuit board, a sensor unit that is disposed on the circuit board and spaced apart from the induction coils and that defines a first reference line with the rotation axis, and a rotor positioning component disposed on the second surface of the base, extending along a second reference line, and capable of magnet attraction with the magnet unit for positioning the rotor unit relative to the sensor unit when the rotor unit stops rotating.
    Type: Grant
    Filed: January 25, 2013
    Date of Patent: May 5, 2015
    Assignee: Yen Sun Technology Corp.
    Inventors: Chien-Jung Chen, Hsien-Wen Liu, Chih-Tsung Hsu, Tzu-Wen Tsai
  • Refractive index tuning of wafer level package LEDs
    Patent number: 9024341
    Abstract: Two or more molded ellipsoid lenses are formed on a packaged LED die by injecting a glue material into a mold over the LED die and curing the glue material. After curing, the refractive index of the lens in contact with the LED die is greater than the refractive index of the lens not directly contacting the LED die. At least one phosphor material is incorporated into the glue material for at least one of the lenses not directly contacting the LED die. The lens directly contacting the LED die may also include one or more phosphor material. A high refractive index coating may be applied between the LED die and the lens.
    Type: Grant
    Filed: October 27, 2010
    Date of Patent: May 5, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiao-Wen Lee, Shang-Yu Tsai, Tien-Ming Lin, Chyi Shyuan Chern, Hsin-Hsien Wu, Fu-Wen Liu, Huai-En Lai, Yu-Sheng Tang
  • METHOD AND APPARATUS FOR GENERATING A DIRECT CURRENT BIAS
    Publication number: 20150115927
    Abstract: A voltage detector operates to detect a system power supply voltage and generate a trigger signal. A control signal generator responds to the trigger signal and generates a control signal. A DC bias generator responds to the control signal by generating a DC bias. The control signal controls the DC bias to have a first value when the power supply voltage is a first voltage and have a second value when the power supply voltage is a second voltage different from the first voltage, wherein the first value is different from the second value. A dynamic DC bias is generated which can not only support a larger voltage scope, but also significantly improves signal to noise ratio. The system power supply detection may concern stop/start operation of an automobile engine.
    Type: Application
    Filed: October 23, 2014
    Publication date: April 30, 2015
    Applicant: STMicroelectronics (Shenzhen) R&D Co. Ltd
    Inventors: Min Chen, Wen Liu, Hong Xia Li
  • ASSEMBLY OF AN ELECTRICAL CONNECTOR AND A CABLE UNIT AND ELECTRONIC DEVICE INCLUDING THE ASSEMBLY
    Publication number: 20150118918
    Abstract: An assembly includes an electrical connector, a cable unit, and adapter terminals. The electrical connector includes an insulator body and conductive terminals disposed at the insulator body. Each conductive terminal includes an insert arm positioned outside the insulator body. The cable unit includes a plug connector and cables connected to the plug connector. Each of the adapter terminals is connected to a core wire of a corresponding cable and is sleeved on the insert arm of a corresponding conductive terminal. Each adapter terminal is electrically connected between the core wire of the corresponding cable and the insert arm of the corresponding conductive terminal.
    Type: Application
    Filed: March 31, 2014
    Publication date: April 30, 2015
    Applicant: WISTRON CORPORATION
    Inventors: Yu-Ju Liu, Che-Wen Liu, Jui-Lin Hsiao
  • ASSEMBLY OF A CIRCUIT BOARD AND A FLEXIBLE FLAT CABLE, CIRCUIT BOARD, AND ASSEMBLING METHOD FOR A FLEXIBLE FLAT CABLE
    Publication number: 20150114694
    Abstract: An assembly includes a circuit board and a flexible flat cable. The circuit board includes a board body having top, bottom and side faces, and a connection module. The board body is formed with a positioning slot that is formed through the top and bottom faces and that has a first length, and an opening that extends from the side face and that is in spatial communication with the positioning slot. The opening is formed through the top and bottom faces and has a second length shorter than the first length. The flexible flat cable includes a connection unit and a cable main body that has a width greater than the second length. The cable main body is able to pass through the opening, and extends through and is positioned in the positioning slot.
    Type: Application
    Filed: March 31, 2014
    Publication date: April 30, 2015
    Applicant: WISTRON CORPORATION
    Inventors: Yu-Ju Liu, Che-Wen Liu
  • Fin Spacer Protected Source and Drain Regions in FinFETs
    Publication number: 20150108544
    Abstract: An integrated circuit device includes a semiconductor substrate, insulation regions extending into the semiconductor substrate, and a semiconductor fin protruding above the insulation regions. The insulation regions include a first portion and a second portion, with the first portion and second portion on opposite sides of the semiconductor fin. The integrated circuit device further includes a gate stack on a top surface and sidewalls of the semiconductor fin, and a semiconductor region connected to an end of the semiconductor fin. The semiconductor region includes a first semiconductor region formed of a first semiconductor material, wherein the first semiconductor region comprise faceted top surfaces, and a second semiconductor region underlying the first semiconductor region. The second semiconductor region has a higher germanium concentration than the first semiconductor region.
    Type: Application
    Filed: October 17, 2013
    Publication date: April 23, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuo-Cheng Ching, Ting-Hung Hsu, Chao-Hsiung Wang, Chi-Wen Liu
  • Passivated and Faceted for Fin Field Effect Transistor
    Publication number: 20150102386
    Abstract: A fin field effect transistor (FinFET), and a method of forming, is provided. The FinFET has a fin having one or more semiconductor layers epitaxially grown on a substrate. A first passivation layer is formed over the fins, and isolation regions are formed between the fins. An upper portion of the fins are reshaped and a second passivation layer is formed over the reshaped portion. Thereafter, a gate structure may be formed over the fins and source/drain regions may be formed.
    Type: Application
    Filed: October 10, 2013
    Publication date: April 16, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yen-Yu Chen, Chi-Yuan Shih, Chi-Wen Liu
  • FinFET with Buried Insulator Layer and Method for Forming
    Publication number: 20150102411
    Abstract: A fin structure suitable for a FinFET and having a buried insulator layer is disclosed. In an exemplary embodiment, a semiconductor device comprises a substrate with a first semiconductor material and having a fin structure formed thereupon. The fin structure includes a lower region proximate to the substrate, a second semiconductor material disposed on the lower region, a third semiconductor material disposed on the second semiconductor material, and an insulating material selectively disposed on the second semiconductor material such that the insulating material electrically isolates a channel region of the fin structure and further such that the insulating material exerts a strain on the channel region. The semiconductor device further comprises an isolation feature disposed adjacent to the fin structure.
    Type: Application
    Filed: October 16, 2013
    Publication date: April 16, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Ching, Guan-Lin Chen, Chao-Hsiung Wang, Chi-Wen Liu
  • MAGNET FIXING STRUCTURE AND ELECTRONIC DEVICE HAVING THE SAME
    Publication number: 20150102193
    Abstract: A magnet fixing structure includes a bottom wall, stopping units, a top wall and an elastic arm. The stopping units are connected to the bottom wall. The top wall is connected to the stopping units. A containing space is formed between the bottom and top walls. The elastic arm disposed on the bottom wall has a protrusion. A passage connected to the containing space is formed between the elastic arm and one stopping unit. When a magnet resists elastic force of the elastic arm to pass the passage along a first axis and partially move into the containing space, parts of the stopping units stop the magnet moving along a second axis, the bottom wall and the top wall stop the magnet moving along a third axis, and the protrusion stops the magnet moving along the first axis. Besides, an electronic device having the magnet fixing structure is also provided.
    Type: Application
    Filed: November 18, 2013
    Publication date: April 16, 2015
    Applicant: Wistron Corporation
    Inventors: Kai-Hsiang Yang, Che-Wen Liu, Yu-Ju Liu
  • MOSFET structure with T-shaped epitaxial silicon channel
    Patent number: 9000526
    Abstract: A MOSFET disposed between shallow trench isolation (STI) structures includes an epitaxial silicon layer formed over a substrate surface and extending over inwardly extending ledges of the STI structures. The gate width of the MOSFET is therefore the width of the epitaxial silicon layer and greater than the width of the original substrate surface between the STI structures. The epitaxial silicon layer is formed over the previously doped channel and is undoped upon deposition. A thermal activation operation may be used to drive dopant impurities into the transistor channel region occupied by the epitaxial silicon layer but the dopant concentration at the channel location where the epitaxial silicon layer intersects with the gate dielectric, is minimized.
    Type: Grant
    Filed: November 3, 2011
    Date of Patent: April 7, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Mahaveer Sathaiya Dhanyakumar, Wei-Hao Wu, Tsung-Hsing Yu, Chia-Wen Liu, Tzer-Min Shen, Ken-Ichi Goto, Zhiqiang Wu
  • FinFETs with Gradient Germanium-Containing Channels
    Publication number: 20150091099
    Abstract: A method includes forming a semiconductor fin, forming a dummy gate on a top surface and sidewalls of the semiconductor fin, and removing the dummy gate to form a recess. The semiconductor fin is exposed to the recess. After the dummy gate is removed, an oxidation is performed on the semiconductor fin to form a condensed germanium-containing fin in the recess, and a silicon oxide layer on a top surface and sidewalls of the condensed germanium-containing fin. The method further includes forming a gate dielectric over the condensed germanium-containing fin, and forming a gate electrode over the gate dielectric.
    Type: Application
    Filed: September 27, 2013
    Publication date: April 2, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Ching, Zhiqiang Wu, Jiun-Jia Huang, Chao-Hsiung Wang, Chi-Wen Liu
  • Method for forming a semiconductor transistor device with optimized dopant profile
    Patent number: 8993424
    Abstract: Provided is a transistor and a method for forming a transistor in a semiconductor device. The method includes performing at least one implantation operation in the transistor channel area, then forming a silicon carbide/silicon composite film over the implanted area prior to introducing further dopant impurities. A halo implantation operation with a very low tilt angle is used to form areas of high dopant concentration at edges of the transistor channel to alleviate short channel effects. The transistor structure so-formed includes a reduced dopant impurity concentration at the substrate interface with the gate dielectric and a peak concentration about 10-50 nm below the surface. The dopant profile also includes the transistor channel having high dopant impurity concentration areas at opposed ends of the transistor channel.
    Type: Grant
    Filed: November 3, 2011
    Date of Patent: March 31, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Wen Liu, Tsung-Hsing Yu, Dhanyakumar Mahaveer Sathaiya, Wei-Hao Wu, Ken-Ichi Goto, Tzer-Min Shen, Zhiqiang Wu
  • Ceiling fan
    Patent number: D726297
    Type: Grant
    Filed: September 4, 2014
    Date of Patent: April 7, 2015
    Assignee: Pan Air Electric Co., Ltd.
    Inventor: Ching-Wen Liu