Patents by Inventor Wen Liu

Wen Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8853287
    Abstract: A functional TFE copolymer fine powder is described, wherein the TFE copolymer is a polymer of TFE and at least one functional comonomer, and wherein the TFE copolymer has functional groups that are pendant to the polymer chain. The functional TFE copolymer fine powder resin is paste extrudable and expandable. Methods for making the functional TFE copolymer are also described. The expanded functional TFE copolymer material may be post-reacted after expansion.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: October 7, 2014
    Assignee: W.L. Gore & Associates, Inc.
    Inventors: Ping Xu, Jack J. Hegenbarth, Rachel Radspinner, Paul D. Drumheller, William B. Johnson, Wen Liu, Xin Kang Chen
  • Publication number: 20140264289
    Abstract: The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a first region and a second region; a first semiconductor mesa formed on the semiconductor substrate within the first region; a second semiconductor mesa formed on the semiconductor substrate within the second region; and a field effect transistor (FET) formed on the semiconductor substrate. The FET includes a first doped feature of a first conductivity type formed in a top portion of the first semiconductor mesa; a second doped feature of a second conductivity type formed in a bottom portion of the first semiconductor mesa, the second semiconductor mesa, and a portion of the semiconductor substrate between the first and second semiconductor mesas; a channel in a middle portion of the first semiconductor mesa and interposed between the source and drain; and a gate formed on sidewall of the first semiconductor mesa.
    Type: Application
    Filed: March 12, 2013
    Publication date: September 18, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Harry-Hak-Lay Chuang, Yi-Ren Chen, Chi-Wen Liu, Chao-Hsiung Wang, Ming Zhu
  • Patent number: 8836084
    Abstract: A crack prevention structure that reduces integrated circuit corner peeling and reduces cracking is disclosed. The crack prevention structure comprises a semiconductor substrate; a first plurality of dielectric layers of a first material disposed over the semiconductor substrate; a second plurality of dielectric layers of a second material different than the first material, disposed on the first plurality of dielectric layers, wherein the first plurality of dielectric layers and the second plurality of dielectric layers meet at an interface; and a plurality of metal structures and a plurality of via structures formed through the interface of the first plurality of dielectric layers and the second plurality of dielectric layers.
    Type: Grant
    Filed: February 11, 2013
    Date of Patent: September 16, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Yu-Wen Liu, Hao-Yi Tsai
  • Publication number: 20140257580
    Abstract: A power line carrier control module includes a microcontroller, an optical coupling isolation unit, a digital input unit, a buffer unit, a digital output unit, an analog-to-digital conversion (ADC) unit, an analog input unit, a digital-to-analog conversion (DAC) unit, an analog output unit, a first power line carrier module and a second power line carrier module. The power line carrier control module can be applied to power line carrier controllers in fields of street light control or industrial control to achieve effects of cross-phase and cross-meter operations in AC 12V to 440V power loops.
    Type: Application
    Filed: March 8, 2013
    Publication date: September 11, 2014
    Inventors: Chin Wen LIU, Kun-Hao Wu
  • Publication number: 20140252442
    Abstract: The present disclosure provides one embodiment of a method of forming a tunnel field effect transistor (TFET). The method includes forming a semiconductor mesa on a semiconductor substrate; performing a first implantation to the semiconductor substrate and the semiconductor mesa to form a drain of a first type conductivity; forming a first dielectric layer on the semiconductor substrate and sidewall of the semiconductor mesa; forming a gate stack on the sidewall of the semiconductor mesa and the first dielectric layer; forming a second dielectric layer on the first dielectric layer and the gate stack; and forming, on the semiconductor mesa, a source having a second type conductivity opposite to the first type conductivity. The gate stack includes a gate dielectric and a gate electrode on the gate dielectric. The source, drain and gate stack are configured to form the TFET.
    Type: Application
    Filed: March 11, 2013
    Publication date: September 11, 2014
    Inventors: Harry-Hak-Lay Chuang, Yi-Ren Chen, Chi-Wen Liu, Chao-Hsiung Wang, Ming Zhu
  • Patent number: 8828823
    Abstract: A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a fin structure including one or more fins disposed on the substrate. The semiconductor device further includes a dielectric layer disposed on a central portion of the fin structure and traversing each of the one or more fins. The semiconductor device further includes a work function metal disposed on the dielectric layer and traversing each of the one or more fins. The semiconductor device further includes a strained material disposed on the work function metal and interposed between each of the one or more fins. The semiconductor device further includes a signal metal disposed on the work function metal and on the strained material and traversing each of the one or more fins.
    Type: Grant
    Filed: April 2, 2014
    Date of Patent: September 9, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Wen Liu, Chao-Hsiung Wang
  • Patent number: 8828796
    Abstract: A semiconductor package and a method of manufacturing the same are provided, the semiconductor package including a first package unit having a first encapsulant and a first semiconductor element, a second package unit having a second encapsulant and a second semiconductor element, a supporting member interposed between the first and second encapsulant, a plurality of conductors penetrating the first encapsulant, the supporting member and the second encapsulant, and redistribution structures disposed on the first and second encapsulants, wherein the first and second encapsulants are coupled with each other by the supporting member to provide sufficient support and protection to enhance the structure strength of the first and second package units.
    Type: Grant
    Filed: November 20, 2013
    Date of Patent: September 9, 2014
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chieh-Yuan Chi, Wei-Yu Chen, Hung-Wen Liu, Yan-Heng Chen, Hsi-Chang Hsu
  • Patent number: 8828842
    Abstract: The present invention in a first aspect proposes a semiconductor structure with a crack stop structure. The semiconductor structure includes a matrix, an integrated circuit and a scribe line. The matrix includes a scribe line region and a circuit region. The integrated circuit is disposed within the circuit region. The scribe line is disposed within the scribe line region and includes a crack stop trench which is disposed in the matrix and adjacent to the circuit region. The crack stop trench is parallel with one side of the circuit region and filled with a composite material in the form of a grid to form a crack stop structure.
    Type: Grant
    Filed: February 5, 2014
    Date of Patent: September 9, 2014
    Assignee: Nanya Technology Corp.
    Inventors: Tse-Yao Huang, Yi-Nan Chen, Hsien-Wen Liu
  • Publication number: 20140240232
    Abstract: A touch device is configured to display a touch activated cursor on a touch screen. The touch device is configured to automatically rotate the cursor depending on movement of the cursor on the touch screen.
    Type: Application
    Filed: December 30, 2013
    Publication date: August 28, 2014
    Applicant: Acer Incorporated
    Inventors: Tsung-Hang Yang, Yu-Hsuan Shen, Yi-Wen Liu
  • Publication number: 20140239396
    Abstract: An embodiment includes a substrate, wherein a portion of the substrate extends upwards, forming a fin, a gate dielectric over a top surface and sidewalls of the fin, a liner overlaying the gate dielectric, and an uninterrupted metallic feature over the liner a portion of the liner overlaying the gate dielectric, wherein the liner extends from a top surface of the uninterrupted metallic feature and covers sidewalls of the metallic feature, and wherein the gate dielectric, liner, and uninterrupted metallic feature collectively form a gate, a gate contact barrier, and a gate contact.
    Type: Application
    Filed: February 27, 2013
    Publication date: August 28, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chi-Wen Liu, Chao-Hsiung Wang
  • Publication number: 20140239354
    Abstract: A finFET and methods for forming a finFET are disclosed. A structure comprises a substrate, a fin, a gate dielectric, and a gate electrode. The substrate comprises the fin. The fin has a major surface portion of a sidewall, and the major surface portion comprises at least one lattice shift. The at least one lattice shift comprises an inward or outward shift relative to a center of the fin. The gate dielectric is on the major surface portion of the sidewall. The gate electrode is on the gate dielectric.
    Type: Application
    Filed: February 27, 2013
    Publication date: August 28, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Lien Huang, Chun-Hsiang Fan, Tsu-Hsiu Perng, Chi-Kang Liu, Yung-Ta Li, Ming-Huan Tsai, Clement Hsingjen Wann, Chi-Wen Liu
  • Patent number: 8816715
    Abstract: A MOS test structure is disclosed. A scribe line region is disposed on a substrate which has a first side and a second side opposite to the first side. An epitaxial layer is disposed on the first side, the doping well is disposed on the epitaxial layer and the doping region is disposed on the doping well. A trench gate of a first depth is disposed in the doping region, in the doping well and in the scribe line region. A conductive material fills the test via which has a second depth and an isolation covering the inner wall of the test via and is disposed in the doping region, in the doping well, in the epitaxial layer and in the scribe line region, to electrically connect to the epitaxial layer so that the test via is capable of testing the epitaxial layer and the substrate together.
    Type: Grant
    Filed: May 12, 2011
    Date of Patent: August 26, 2014
    Assignee: Nanya Technology Corp.
    Inventors: Chin-Te Kuo, Yi-Nan Chen, Hsien-Wen Liu
  • Patent number: 8819184
    Abstract: A method and a system for playing a multimedia file and a computer readable medium using the method are provided. In the present invention, a control apparatus sends a control command to a destination apparatus. A multimedia playing module in the destination apparatus is enabled according to the control command. And a response message is sent to the control apparatus by the destination apparatus after receiving the controlling command. Afterwards, the control apparatus transmits the multimedia file to the destination apparatus in a streaming mode for playing the multimedia file through the multimedia playing module.
    Type: Grant
    Filed: April 15, 2011
    Date of Patent: August 26, 2014
    Assignee: Acer Incorporated
    Inventors: Kuan-Chieh Huang, Yuan-Peng Wang, Yi-Wen Liu
  • Patent number: 8810025
    Abstract: The present disclosure provides a carrier substrate, a device including the carrier substrate, and a method of bonding the carrier substrate to a chip. An exemplary device includes a carrier substrate having a chip region and a periphery region, and a chip bonded to the chip region of the carrier substrate. The carrier substrate includes a reinforcement structure embedded within the periphery region.
    Type: Grant
    Filed: March 17, 2011
    Date of Patent: August 19, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Wen Liu, Ching-Jung Yang, Hsien-Wei Chen, Hsin-Yu Pan, Chao-Wen Shih
  • Patent number: 8808911
    Abstract: A cathode composite material includes a cathode active material and a coating layer coated on a surface of the cathode active material. The cathode active material includes a layered type lithium transition metal oxide. A material of the coating layer is a lithium metal oxide having a crystal structure belonging to C2/c space group of the monoclinic crystal system. The present disclosure also relates to a lithium ion battery including the cathode composite material.
    Type: Grant
    Filed: November 30, 2012
    Date of Patent: August 19, 2014
    Assignees: Tsinghua University, Hon Hai Precision Industry Co., Ltd.
    Inventors: Ya-Dong Li, Jun Lu, Ding-Sheng Wang, Xiang-Wen Liu, Qing Peng
  • Patent number: 8807429
    Abstract: A recognition system is offered. The recognition system is for sensing a plurality of units under test of at least an object under test. The recognition system comprises a periodic guided-wave structure and a near field sensing device. The periodic guided-wave structure is disposed under the object under test and has a plurality of conductive units periodically arranged on a plane. The near field sensing device has a near field antenna and senses the plurality of units under test through detecting the near field magnetic field. The periodic guided-wave structure confines the electromagnetic field for facilitating to determine the distance from any one of the units under test to the periodic guided-wave structure.
    Type: Grant
    Filed: June 16, 2012
    Date of Patent: August 19, 2014
    Assignee: Auden Techno Corp.
    Inventor: Hsien-Wen Liu
  • Patent number: 8801224
    Abstract: The present invention provides an LED illumination device including a base, at least one flexible circuit board and a plurality of LEDs. The at least one flexible circuit board is used for covering the base. The LEDs are mounted on the flexible circuit board. The present invention utilizes a flexible circuit board that can conform to the base having a 360 degree curved surface and a 3D solid structure to efficiently change the viewing angle of the LEDs so as to provide 360 degree viewing angle. Furthermore, a single flexible circuit board can be utilized to cover the base to provide a 360 degree viewing angle. Therefore, the LED illumination device of the present invention can reduce manufacturing cost and simplify the manufacturing process.
    Type: Grant
    Filed: June 9, 2011
    Date of Patent: August 12, 2014
    Assignee: Parlux Optoelectronics Co., Ltd.
    Inventors: Tang-Chieh Huang, Yu-Tang Yen, Ching-Hao Chang, Bing-You Weng, Sunao Hsu, Yao-Wen Liu
  • Patent number: 8803223
    Abstract: An improved semiconductor device is provided whereby the semiconductor device is defined by a layered structure comprising a first dielectric layer, a data storage material disposed on the first dielectric layer, and a second dielectric layer disposed on the data storage material, the layered structured substantially forming the outer later of the semiconductor device. For example, the semiconductor device may be a SONOS structure having an oxide-nitride-oxide (ONO) film that substantially surrounds the SONOS structure. The invention also provides methods for fabricating the semiconductor device and the SONOS structure of the invention.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: August 12, 2014
    Assignee: Macronix International Co., Ltd.
    Inventors: Ching-Chang Lin, Kai-Hsiang Chang, Chih-Yuan Wu, Kuang-Wen Liu
  • Publication number: 20140219397
    Abstract: Systems and methods for frequency offset estimation are provided. A channel impulse response and multi-user signal parameter are jointly estimated. Based on the multi-user signal parameter, a determination is made as to whether the signal contains a single-user signal or a multi-user signal. Then, frequency offset estimation is performed based on this determination. For example, noiseless sample estimates are generated depending on whether the signal is a single-user signal or a multi-user signal.
    Type: Application
    Filed: February 4, 2013
    Publication date: August 7, 2014
    Applicant: RESEARCH IN MOTION LIMITED
    Inventors: DAYONG CHEN, YI WEN LIU
  • Patent number: 8796666
    Abstract: A device includes a substrate, insulation regions extending into the substrate, and a semiconductor fin higher than top surfaces of the insulation regions. The semiconductor fin has a first lattice constant. A semiconductor region includes sidewall portions on opposite sides of the semiconductor fin, and a top portion over the semiconductor fin. The semiconductor region has a second lattice constant different from the first lattice constant. A strain buffer layer is between and contacting the semiconductor fin and the semiconductor region. The strain buffer layer includes an oxide.
    Type: Grant
    Filed: April 26, 2013
    Date of Patent: August 5, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Lien Huang, Tung Ying Lee, Chung-Hsien Chen, Chi-Wen Liu