Abstract: An embodiment of the disclosure includes a method of fabricating a plurality of light emitting diode devices. A plurality of LED dies is provided. The LED dies are bonded to a carrier substrate. A patterned mask layer comprising a plurality of openings is formed on the carrier substrate. Each one of the plurality of LED dies is exposed through one of the plurality of the openings respectively. Each of the plurality of openings is filled with a phosphor. The phosphor is cured. The phosphor and the patterned mask layer are polished to thin the phosphor covering each of the plurality of LED dies. The patterned mask layer is removed after polishing the phosphor.

Abstract: The present invention relates to a method for detecting a blank area of a power calibration area. The method includes the steps of: selecting a recording test area in the power calibration area; writing the recording test area with multiple stages of normal power and detecting power; forming multiple normal blocks and detecting blocks, wherein each of the detecting blocks includes one unit of unrecorded block and one unit of recorded block; and reading information from the unrecorded blocks of the detecting blocks and thus determining whether the unrecorded blocks of the detecting blocks are blank or not. Once all the unrecorded blocks of the detecting blocks are determined to be blank, it represents that the selected recording test area is totally blank.

Abstract: The present disclosure provides a carrier substrate, a device including the carrier substrate, and a method of bonding the carrier substrate to a chip. An exemplary device includes a carrier substrate having a chip region and a periphery region, and a chip bonded to the chip region of the carrier substrate. The carrier substrate includes a reinforcement structure embedded within the periphery region.

Abstract: In an optimal recording power calibration method for improving seeking stability on a recording power calibration area, a specific area serves as a data recording area during an optimal recording power calibration, wherein a length of the specific area is such that a plurality of times of optimal recording power calibrations can be performed. The method includes: an optimal recording power calibration step of recording, with different recording power, a first length of calibration data in the specific area, and calibrating optimal recording power, wherein a data sector recorded in this step is defined as a calibration recording sector; and a data recording step of recording, with data recording power, a second length of information having a logical address beside the calibration recording sector of the specific area, wherein a data sector recorded in the step is defined as an information recording sector.

Abstract: A system and method for real-time network communications provides a session identifier as a public key for group communication between clients, and provides a channel identifier representing a private key for each of a plurality of clients. The channel identifier includes client-specific attributes, which function to indicate grouping criteria for the group communication. A dynamic communication link is created over a network between a client and a service based upon the public and private key combination such that group communication is enabled based upon the attributes of the private key and the public key. Communications are translated using a translation service which employs the attributes associated with the private key and the public key combination to provide response information in a designated language to enable multi-lingual real-time communications.

Abstract: The present invention relates to methods for on-line calibrating output power of an optical pick-up. A power adjusting circuit of the optical pick-up has an optical power regulator and an optical power detector. The on-line output power calibrating method includes the steps of: performing a recording pre-process; providing a focus offset value and/or a tilt offset value to the optical pick-up; providing a setting value, corresponding to power under test, to the optical power regulator; detecting laser power emitted from the optical pick-up using the optical power detector; comparing the laser power with the power under test to adjust the setting value of the optical power regulator corresponding to the power under test; and performing an optimum power calibration if the laser power emitted from the optical pick-up conforms to the power under test.

Abstract: A method for preparation of N-methyl-3-(2-tributylstannylphenoxy)-3-phenylpropanamine is provided, which includes formation of N-methyl-3-(2-tributylstannylphenoxy)-3-phenylpropanamine, useful as a precursor of a norepinephrine transporter (NET) contrast label [123Iodine](R)—N-methyl-3-(2-iodophenoxy)-3-phenylpropanamine ([123I]MIPP) with a leaving group Bu3Sn.

Abstract: A method of forming a trench by a silicon-containing mask is provided in the present invention. The method includes providing a substrate covered with a silicon-containing mask. Then, anti-etch dopants are implanted into the silicon-containing mask to transform the silicon-containing mask into an etching resist mask. Later, the substrate and the etching resist mask are patterned to form at least one trench. Next, a silicon-containing layer is formed to fill into the trench. Finally, the silicon-containing layer is etched by taking the etching resist mask as a mask.

Abstract: A bonding pad structure is provided that includes two conductive layers and a connective layer interposing the two conductive layers. The connective layer includes a contiguous, conductive structure. In an embodiment, the contiguous conductive structure is a solid layer of conductive material. In other embodiments, the contiguous conductive structure is a conductive network including, for example, a matrix configuration or a plurality of conductive stripes. At least one dielectric spacer may interpose the conductive network. Conductive plugs may interconnect a bond pad and one of the conductive layers.

Abstract: A master-slave mobile communication system includes a host device and an extension device. The host device includes a call module, a first BLUETOOTH® module and a first communication module. The extension device includes a second BLUETOOTH® module and a second communication module. The first and second communication modules log in to a first and a second network domain respectively. The first and second BLUETOOTH® modules provide an information channel between the host device and the extension device to transmit a data. The extension device informs the host device a login data of the second network domain. The host device communicates with a remote device through the first network domain or the information channel and the second network domain that the extension device logs into. Therefore, in a specific range, the host device uses functions of the extension device and a BLUETOOTH® technology to log in to two network domains.

Abstract: A high-order harmonic device of a cavity filter including a base and a lid cover the base is disclosed. The base has a through groove connecting to an upper and a lower portion. The base has a plurality of output terminal with metallic conductor extending into the inner side formed on the surface of the sidewall. The base has resonance space formed indented to receive the metallic conductor and extending to connect to the through groove. The lid has a plurality of threading holes formed corresponding to chambers and partitions received with adjusting elements for height adjustment. The adjusting elements has the resonance bars corresponding to every chamber and the suppressing bars corresponding to every partition. By adjusting suppressing bar and the partition to a predetermined distance, the space of the channel for transmitting the high-order harmonic wave can be reduced to suppress noise produced by high-order harmonic wave.

Abstract: A manufacturing method for a vertical transistor of random-access memory, having the steps of: defining an active region on a semiconductor substrate; forming a shallow trench isolation structure outside of the active region; etching the active region and forming a gate dielectric layer and a positioning gate thereon, forming a word line perpendicular to the positioning gate; forming spacing layers on the outer surfaces of the word line; implanting ions to the formed structure in forming an n-type and a p-type region on opposite sides of the word line with the active region; forming an n-type and a p-type floating body respectively on the n-type and p-type region; forming a source line perpendicular to the word line and connecting to the n-type floating body; forming a bit line perpendicular to the source line and connecting to the p-type floating body. Hence, a vertical transistor with steady threshold voltage is achieved.

Abstract: A semiconductor package structure is provided. The structure includes a semiconductor chip having a plurality of interconnect layers formed thereover. A first passivation layer is formed over the plurality of interconnect layers. A stress buffer layer is formed over the first passivation layer. A bonding pad is formed over the stress buffer layer. A second passivation layer is formed over a portion of the bonding pad, the second passivation having at least one opening therein exposing a portion of the bonding pad.

Abstract: Various embodiments are described herein that make use of a lost frame concealment method for processing data frames received from transmission over a communications channel. The method involves determining whether a current data frame is a bad frame, performing source decoding on the current data frame with one or more parameters that are limited by a first set of one or more values if the current data frame is a bad frame, and performing source decoding on the current data frame with one or more parameters that are not limited if the current data frame is a good frame.

Abstract: A semiconductor device includes a substrate having a circuit region and a seal ring region. The seal ring region surrounds the circuit region. A seal ring structure is disposed over the seal ring region. The seal ring structure has a first portion and a second portion above the first portion. The first portion has a width W1, and the second portion has a width W2. The width W1 is less than the width W2.

Abstract: A mobile phone utilizes a radio frequency (RF) chip transceiving RF signals via a front end circuit. A power detector detects power output from a power amplifier and converts the power to voltage to transmit to a central processing unit (CPU). A base station tester measures output power of the mobile phone and transmits to the CPU in a test mode. A microwave chamber measures power radiated by the antenna in an operation mode. A high voltage circuit provides a high voltage signal continuously. A detection circuit detects a connection status of the base station tester and the testing connector and outputs the high voltage signal to the CPU according to the connection status. The CPU determines an operating mode of the mobile phone based on output of the detection circuit, and outputs a maximum output power according to the test mode and operation mode maximum output power calibration tables.

Abstract: A fastening type heat-dissipation structure for connecting a light-emitting module to an enclosure includes a first fixing member and a second fixing member separately attached to two opposite inner sides of the enclosure; and a flat plate, on which the light-emitting module is mounted. The flat plate is provided with at least a first extended section and at least a second extended section for abutting on and locking to the first and the second fixing member, respectively, so that the flat plate is firmly mounted in the enclosure via the fixing members. And, heat produced by the light-emitting module mounted on the flat plate can be transferred via the extended sections and the fixing members to the enclosure and dissipated from the enclosure into ambient air to enable largely upgraded heat-dissipation effect.

Abstract: A capacitor structure and a manufacturing method thereof. The capacitor structure includes a first conductor layer, a dielectric layer and a second conductor layer. The first conductor layer has a first metal material and a second metal material. The first metal material is formed with voids and the second metal material is filled in the voids via hot melt. Accordingly, in the first conductor layer, the second metal material is filled into the voids of the first metal material by means of hot melt to bond with the first metal material. In this case, the thermal treatment temperature can be effectively lowered and the electrical conductivity of the capacitor structure can be increased. Also, the strength of the capacitor structure is increased.

Abstract: A motor stator includes a stator unit and an auxiliary induction unit. The stator unit includes a circuit substrate, and a plurality of induction coils embedded within the circuit substrate. The auxiliary induction unit includes an insulating member, a magnetic conductor, and at least one coil winding assembly. The coil winding assembly includes a conductive rod and an auxiliary coil. The rod has an insert rod section extending through the magnetic conductor, the insulating member, and the circuit substrate, and a wound rod section permitting the auxiliary coil to be wound thereon, such that the auxiliary coil is disposed outwardly of the magnetic conductor. During assembly, the induction coil assembly is mounted to the magnetic conductor, and the insulating member is superposed on the circuit substrate. Subsequently, the rod is inserted through the insulating member and into the circuit substrate.