Abstract: An optical lens is provided in the present invention. The optical lens includes a first curved surface and an annular mask component on and in direct contact with the first curved surface, wherein the annular mask component shields a peripheral annular region of the optical lens from entry of light. The present invention further provides an optical microscope system using the same.

Abstract: The protuberant structure of the present invention includes a substrate and a protrusion disposed on the substrate. The protrusion has a top side, a bottom side and a tapered side wall disposed between the top side and the bottom side. The top side has an extremely small top width which is not greater than 32 nm.

Abstract: A wafer cleaning method includes: (1) providing a wafer cleaning apparatus comprising a sponge for scrubbing a surface of a semiconductor wafer to be cleaned; (2) implementing a pre-conditioning flow to pre-condition the sponge using a dummy wafer; and (3) performing a regular cleaning flow to scrub the surface of the semiconductor wafer to be cleaned using the pre-conditioned sponge. The dummy wafer has a plurality of upward protruding features on a surface of the dummy wafer for removing residual fibers or unwanted substances from the sponge.

Abstract: A semiconductor process is provided. A substrate is provided in an etching apparatus, wherein first conductive patterns, a barrier layer and a patterned insulating layer are formed thereon. The first openings are formed between the first conductive patterns, the barrier layer covers surfaces of the first conductive patterns and the first openings, and the patterned insulating layer is formed on the first conductive patterns and has a plurality of second openings. The second openings expose the barrier layer on top corners of the first conductive patterns. Polymer layers are formed on the barrier layer, wherein a thickness of the polymer layer on the top corners of the first conductive pattern is larger than a thickness of the polymer layer on bottom portions of the first openings. An etching process is performed to remove the polymer layer and the barrier layer disposed on the bottom portions of the first openings.

Abstract: A method for increasing adhesion between polysilazane and silicon nitride is disclosed, comprising, providing a substrate comprising a trench, forming a silicon nitride liner layer on a bottom surface and a sidewall of the trench, performing a treating process to the silicon nitride liner layer for producing a hydrophilic surface with OH groups that can increase adhesion between the silicon nitride liner layer and a subsequently formed polysilazane coating layer, and forming a polysilazane coating layer into the trench and on the silicon nitride liner layer.

Abstract: A method for fabricating a gate dielectric layer comprises the steps of: forming a dielectric layer on a semiconductor substrate; performing a nitrogen treating process to form a nitride layer on the dielectric layer; and performing a thermal treating process at 1150-1400° C. for a period of 400-800 milliseconds, to form a gate dielectric layer. A step of forming a gate layer on the gate dielectric layer may be performed to form a gate structure.

Abstract: A method of forming a buried bit line is provided. A substrate is provided and a line-shaped trench region is defined in the substrate. A line-shaped trench is formed in the line-shaped trench region of the substrate. The line-shaped trench includes a sidewall surface and a bottom surface. Then, the bottom surface of the line-shaped trench is widened to form a curved bottom surface. Next, a doping area is formed in the substrate adjacent to the curved bottom surface. Lastly, a buried conductive layer is formed on the doping area such that the doping area and the buried conductive layer together constitute the buried bit line.

Abstract: An integrated circuit structure including a copper-aluminum interconnect with a barrier layer including a titanium nitride layer and a method for fabricating the same are disclosed. The method for fabricating an integrated circuit structure including a copper-aluminum interconnect according to the present invention comprises the steps of providing a copper (Cu) layer; forming a barrier layer connected to the copper layer, wherein the barrier layer comprises a first layer including a tantalum layer and a tantalum nitride layer and a second layer including a titanium nitride layer, the first layer contacts the copper layer and is disposed between the copper layer and the second layer, and the barrier layer has a recess correspondingly above the copper layer; and forming an aluminum (Al) layer disposed in the recess.

Abstract: A method for forming a trench isolation is disclosed, comprising, providing a substrate comprising a trench, forming a polysilicon layer in the trench, and subjecting the substrate to a treating process to convert the polysilicon layer to an isolating layer, wherein the treating process is fine tuned for the isolating layer on opposite sidewalls of the trench to expand to contact with each other so that the isolating layer fills the trench.

Abstract: A method for fabricating a gate dielectric layer comprises the steps of: forming a dielectric layer on a semiconductor substrate; performing a nitrogen treating process to form a nitride layer on the dielectric layer; performing an oxygen treating process to implant oxygen into the nitride layer; and performing a thermal treating process to form a gate dielectric layer. A step of forming a gate layer on the gate dielectric layer may be performed to form a gate structure.

Abstract: An integrated circuit structure including a copper-aluminum interconnect with a CuSiN layer and a method for fabricating the same are provided. The method for fabricating an integrated circuit structure including a copper-aluminum interconnect according to the present invention comprises the steps of providing a copper (Cu) layer; forming a barrier layer including a CuSiN layer on the copper layer; forming a wetting layer on the barrier layer; and forming an aluminum (Al) layer on the wetting layer.

Abstract: A method of oxidizing polysilazane is disclosed, comprising providing a substrate, comprising a trench, forming a polysilazane layer in the trench, and treating the polysilazane layer in an acid containing solution applied with mega-sonic waves to oxidize the polysilazane layer, wherein the acid containing solution comprises phosphoric acid, sulfuric acid, H2SO4 added with O3 (SOM), H2SO4 added with H2O2 (SPM), H3PO4 added with O3, or H3PO4 added with H2O2, and removing the silicon oxide layer outside of the trench.

Abstract: A method for fabricating a conductive contact is provided, including: providing a semiconductor substrate with a dielectric layer formed thereover and two conductive regions and an isolation element formed therein, wherein the isolation element isolates the two conductive regions from each other; forming an opening in the dielectric layer, exposing a top surface of the isolation element and a portion of a top surface of each of the conductive regions; performing an epitaxy process and forming a conductive semiconductor layer within the opening, overlying the top surface of the isolation element and the portion of the top surface of each of the conductive regions; and forming a conductive layer in the opening, overlying the conductive semiconductor layer and filling the opening.

Abstract: A method for staining a sample includes the following steps. A test device is provided. The test device is sampled to obtain a sample. The sample includes a substrate, an active area disposed within the substrate and having a first doped substrate region and a second doped substrate region, at least one gate disposed between the first doped substrate region and the second doped substrate region, and an exposed shallow trench isolation embedded in the substrate and surrounding the active area. A first staining procedure is then carried out to selectively remove the shallow trench isolation to form a first void and to entirely expose the active area. A second staining procedure is subsequently carried out to selectively stain the first doped substrate region and the second doped substrate region to form a second void.

Abstract: A manufacturing method of a gate dielectric layer that includes a nitride layer and an oxide layer is provided. A substrate is provided. A nitridation treatment is performed to form the nitride layer on the substrate. An oxidation treatment is performed subsequent to the formation of the nitride layer to form the oxide layer between the nitride layer and the substrate.

Abstract: A polishing pad wear detecting apparatus suitable for a chemical mechanical polishing (CMP) apparatus is provided. The polishing pad wear detecting apparatus includes an arm and a height detector. One end of the arm is fastened on the CMP apparatus. The height detector is disposed on the arm for detecting height variation of a polishing pad.

Abstract: A method of bevel trimming a three dimensional (3D) semiconductor device is disclosed, comprising providing a substrate with stack layers thereon and through substrate vias (TSV) therein, wherein an edge of the substrate is curved, performing a bevel trimming step to the curved edge of the substrate for obtaining a planar edge, and thinning the substrate to expose the through substrate vias.

Abstract: An integrated circuit with a self-aligned contact includes a substrate with a transistor formed thereover, a dielectric spacer, a protection barrier, and a conductive layer. The transistor includes a mask layer and a pair of insulating spacers formed on opposite sides of the mask layer. The dielectric spacer partially covers at least one of the insulating spacers of the transistor. The protection barrier is formed over the dielectric spacer. The conductive layer is formed over the mask layer, the protection barrier, the dielectric spacer, the insulating spacer and the dielectric spacer as a self-aligned contact for contacting a source/drain region of the transistor.

Abstract: A capacitor and a manufacturing method thereof are provided. The capacitor includes a first electrode, a first metal layer, a dielectric layer and a second electrode. The first electrode is disposed on a substrate. The first metal layer is disposed on the first electrode. The dielectric layer is disposed on the first metal layer, wherein the material of the first metal layer does not react with the material of the dielectric layer. The second electrode is disposed on the dielectric layer.

Abstract: A manufacturing method of a gate dielectric layer is provided. An oxidation treatment is performed to form an oxide layer on a substrate. A nitridation treatment is performed to form a nitride layer on the oxide layer. An annealing treatment is performed in a mixing gas of N2 and O2, where the temperature of the annealing treatment is 900° C. to 950° C., the pressure of the annealing treatment is 5 Torr to 10 Torr, and the content ratio of the N2 to O2 is 0.5 to 0.8.