Patents by Inventor Wen Liu

Wen Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120313243
    Abstract: A chip-scale package includes an encapsulating layer, a chip embedded in the encapsulating layer and having an active surface exposed from the encapsulating layer, a buffering dielectric layer formed on the encapsulating layer and the chip, a build-up dielectric layer formed on the buffering dielectric layer, and a circuit layer formed on the build-up dielectric layer and having conductive blind vias penetrating the build-up dielectric layer and being in communication with the openings of the buffering dielectric layer and electrically connected to the chip, wherein the build-up dielectric layer and the buffering dielectric layer are made of different materials. Therefore, delamination does not occur between the buffering dielectric layer and the encapsulating layer, because the buffering dielectric layer is securely bonded to the encapsulating layer and the buffering dielectric layer is evenly distributed on the encapsulating layer.
    Type: Application
    Filed: August 30, 2011
    Publication date: December 13, 2012
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chiang-Cheng Chang, Hung-Wen Liu, Hsi-Chang Hsu, Hsin-Yi Liao, Shih-Kuang Chiu
  • Publication number: 20120316164
    Abstract: The present invention provides a method for inhibiting the growth of cancer stem cells, particularly colorectal cancer stem cells, liver cancer stem cells, lung cancer stem cells or breast cancer stem cells, comprising administering to a subject in need thereof a therapeutically effective amount of a compound of antimycin A or a pharmaceutically acceptable salt thereof, together with a pharmaceutically acceptable carrier.
    Type: Application
    Filed: June 13, 2011
    Publication date: December 13, 2012
    Inventors: CHI-YING HUANG, CHI-TAI YEH, CHUN-HUNG WU, YU-WEN LIU
  • Patent number: 8329879
    Abstract: H3LMN series compounds used as radioactive agents for treatment of liver cancer and a manufacturing method thereof are revealed. 2-thioethylamine hydrochloride is reacted with triphenylmethanol for protection of thiol to obtain 2-[(triphenylmethyl)thio]ethylamine. Then obtain N-[2-((triphenylmethyl)thio)ethyl]chloroacetamide by a transamidation reaction between 2-[(triphenylmethyl)thio]ethylamine and chloroactyl chloride. Next produce a amine-amide-thiol ligand-N-[2-((triphenylmethyl)thio)ethyl][2-((triphenylmethyl)thio)ethylamino]acetamide by a substitution reaction of N-[2-((triphenylmethyl)thio)ethyl]chloroacetamide and 2-[(triphenylmethyl)thio]ethylamine. After respective reaction with 1-bromotetradecane, 1-bromohexadecane and ethyl 16-bromohexadecanoate, H3LMN series compounds are obtained. These amine-amide-dithiols quadridentate ligands can react with MO3+ (M=Tc or Re) to produce electrically neutral complexes.
    Type: Grant
    Filed: September 14, 2009
    Date of Patent: December 11, 2012
    Assignee: Atomic Energy Council-Institute of Nuclear Energy Research
    Inventors: Show-Wen Liu, Cheng-Hsien Lin, Tsyh-Lang Lin, Cheng-Fang Hsu
  • Publication number: 20120309192
    Abstract: A semiconductor process is provided. A mask layer is formed on a substrate and has a first opening exposing a portion of the substrate. Using the mask layer as a mask, a dry etching process is performed on the substrate to form a second opening therein. The second opening has a bottom portion and a side wall extending upwards and outwards from the bottom portion, wherein the bottom portion is exposed by the first opening and the side wall is covered by the mask layer. Using the mask layer as a mask, a vertical ion implantation process is performed on the bottom portion. A conversion process is performed, so as to form converting layers on the side wall and the bottom portion of the second opening, wherein a thickness of the converting layer on the side wall is larger than a thickness of the converting layer on the bottom portion.
    Type: Application
    Filed: June 6, 2011
    Publication date: December 6, 2012
    Applicant: NANYA TECHNOLOGY CORPORATION
    Inventors: Wen-Chieh Wang, Yi-Nan Chen, Hsien-Wen Liu
  • Publication number: 20120309155
    Abstract: A semiconductor process is provided. A substrate is provided, gates each including a silicon layer, a silicide layer and a cap layer are formed thereon, and doped regions are formed at two sides of each gate. An insulating layer is formed to cover a memory region and a periphery region. First contact holes are formed in the insulating layer in the memory region, and each first contact hole is disposed between the two adjacent gates and exposes the doped region. A contact plug is formed in each first contact hole to electrically connect the doped region. A patterned mask layer is formed on the substrate to cover the memory region and expose a portion of the periphery region. Using the patterned mask layer as a mask, second and third contact holes are formed in the insulating layer in the periphery region, to expose the silicide layer and the doped region.
    Type: Application
    Filed: June 3, 2011
    Publication date: December 6, 2012
    Applicant: NANYA TECHNOLOGY CORPORATION
    Inventors: Wen-Chieh Wang, Yi-Nan Chen, Hsien-Wen Liu
  • Publication number: 20120305525
    Abstract: A method of reducing striation on a sidewall of a recess is provided. The method includes the steps of providing a substrate covered with a photoresist layer. Then, the photoresist layer is etched to form a patterned photoresist layer. Later, a repairing process is performed by treating the patterned photoresist layer with a repairing gas which is selected from the group consisting of CF4, HBr, O2 and He. Next, the substrate is etched by taking the patterned photoresist layer as a mask after the repairing process. Finally, the patterned photoresist layer is removed.
    Type: Application
    Filed: May 31, 2011
    Publication date: December 6, 2012
    Inventors: Hsiu-Chun Lee, Yi-Nan Chen, Hsien-Wen Liu
  • Publication number: 20120305956
    Abstract: The present disclosure provides a method of patterning a phosphor layer on a light emitting diode (LED) emitter. The method includes providing at least one LED emitter disposed on a substrate; forming a polymer layer over the at least one LED emitter; providing a mask over the polymer layer and the at least one LED emitter; etching the polymer layer through the mask to expose the at least one LED emitter within a cavity having polymer layer walls; and coating the at least one LED emitter with phosphor.
    Type: Application
    Filed: June 1, 2011
    Publication date: December 6, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Fu-Wen Liu, Chyi Shyuan Chern, Hsin-Hsien Wu, Yung-Chang Chen, Ming Shing Lee, Tzu-Wen Shih, Hsin-Hung Chen
  • Publication number: 20120301833
    Abstract: The present invention provides a method of reducing microloading effect by using a photoresist layer as a buffer. The method includes: providing a substrate defined with a dense region and an isolated region. Then, a dense feature pattern and an isolated feature pattern are formed on the dense region and the isolated region respectively. After that, a photoresist layer is formed to cover the isolated region. Finally, the substrate and the photoresist layer are etched by taking the dense feature pattern and the isolated feature pattern as a mask.
    Type: Application
    Filed: May 29, 2011
    Publication date: November 29, 2012
    Inventors: Hsiu-Chun Lee, Yi-Nan Chen, Hsien-Wen Liu
  • Publication number: 20120302049
    Abstract: The disclosure provides a method for wafer implantation including the following steps: providing a wafer, wherein the wafer comprises a central circular portion, and a peripheral annular portion adjacent to a edge of the wafer, and wherein the central circular portion and the peripheral annular portion are concentric; and implanting ion beams into the wafer, wherein the central circular portion has a first average implantation dose and the peripheral annular portion has a second average implantation dose, and the first average implantation dose and the second first average implantation dose are different.
    Type: Application
    Filed: May 24, 2011
    Publication date: November 29, 2012
    Applicant: NANYA TECHNOLOGY CORPORATION
    Inventors: Ping Hsu, Yi-Nan Chen, Hsien-Wen Liu
  • Publication number: 20120298992
    Abstract: A test layout structure includes a substrate, a first oxide region of a first height, a second oxide region of a second height, a plurality of border regions, and a test layout pattern. The first oxide region is disposed on the substrate. The second oxide region is also disposed on the substrate and adjacent to the first oxide region. The first height is substantially different from the second height. A plurality of border regions are disposed between the first oxide region and the second oxide region. The test layout pattern includes a plurality of individual sections. A test region is disposed between two of the adjacent individual sections which are parallel to each other.
    Type: Application
    Filed: May 26, 2011
    Publication date: November 29, 2012
    Inventors: Chin-Te Kuo, Yi-Nan Chen, Hsien-Wen Liu
  • Publication number: 20120302060
    Abstract: The disclosure provides a method for manufacturing a memory device, including: providing a plurality of gate structures formed on a substrate, wherein the gate structures comprise a cap layer disposed on the top of the gate structure, and each two adjacent gate structures are separated by a gap; blanketly forming a polysilicon layer on the substrate to fill the gap; performing a planarization process to the polysilicon layer, obtaining a polysilicon plug; and performing an oxidation process after the planarization process, converting a part of the polysilicon plug and a residual polysilicon layer over the gate structure to silicon oxide.
    Type: Application
    Filed: May 24, 2011
    Publication date: November 29, 2012
    Applicant: NANYA TECHNOLOGY CORPORATION
    Inventors: Ping Hsu, Yi-Nan Chen, Hsien-Wen Liu
  • Publication number: 20120299185
    Abstract: A slit recess channel gate is further provided. The slit recess channel gate includes a substrate, a gate dielectric layer, a first conductive layer and a second conductive layer. The substrate has a first trench. The gate dielectric layer is disposed on a surface of the first trench and the first conductive layer is embedded in the first trench. The second conductive layer is disposed on the first conductive layer and aligned with the first conductive layer above the main surface, wherein a bottom surface area of the second conductive layer is substantially smaller than a top surface area of the second conductive layer. The present invention also provides a method of forming the slit recess channel gate.
    Type: Application
    Filed: May 27, 2011
    Publication date: November 29, 2012
    Inventors: Tieh-Chiang Wu, Yi-Nan Chen, Hsien-Wen Liu
  • Publication number: 20120299668
    Abstract: A cavity filter includes a base member defining therein a resonant chamber, an antenna port disposed at the center of the resonant chamber, two signal input/output ports respectively disposed at two distal ends of the resonant chamber for signal input/output, a cover member covering the base member, two feedback channels disposed in the base member at two opposite lateral sides relative to the resonant chamber and respectively connected between the signal ports and the antenna port, and wave-absorbing components respectively mounted in the feedback channels for removing surge waves from feedback frequency components in the feedback channels.
    Type: Application
    Filed: May 25, 2011
    Publication date: November 29, 2012
    Inventors: Hsien-Wen LIU, Chien-Chih LEE, Chin-Hsuan TSAI, Shang-Yu YANG
  • Publication number: 20120302065
    Abstract: The present invention relates to a pulse-plasma etching method and apparatus for preparing a depression structure with reduced bowing. The pulse-plasma etching apparatus comprises a container, an upper electrode plate, a lower electrode plate, a gas source, a first ultrahigh RF power supply, a bias RF power supply, and a pulsing module. When the pulsing module supplies an ultrahigh-frequency voltage between the upper electrode plate and the lower electrode plate, an ultrahigh-frequency voltage is switched to the off state, and a large amount of electrons pass through the plasma and reach the substrate to neutralize the positive ions during the duration of the off state (Toff).
    Type: Application
    Filed: May 26, 2011
    Publication date: November 29, 2012
    Applicant: NANYA TECHNOLOGY CORPORATION
    Inventors: Chih Ching Lin, Yi Nan Chen, Hsien Wen Liu
  • Publication number: 20120302031
    Abstract: The present invention relates to a plasma etching method and apparatus for preparing high-aspect-ratio structures. The method includes the steps of placing the substrate into a plasma etching apparatus, wherein the plasma etching apparatus includes an upper electrode plate and a lower electrode plate; continuously supplying an upper source RF power and a DC power to the upper electrode plate; and discontinuously supplying a bias RF power to the lower electrode plate. When the bias RF power is switched to the off state, a large amount of secondary electrons pass through the bulk plasma and reach the substrate to neutralize the positive ions during the duration time of the off state (Toff).
    Type: Application
    Filed: May 23, 2011
    Publication date: November 29, 2012
    Applicant: NANYA TECHNOLOGY CORPORATION
    Inventors: Chang Ming Wu, Yi Nan Chen, Hsien Wen Liu
  • Publication number: 20120302070
    Abstract: A method for performing pulse-etching in a semiconductor device includes the steps of providing a semiconductor substrate, wherein a metal layer is disposed on the semiconductor substrate, and a hard mask layer is blanketed over the metal layer; introducing the semiconductor substrate into a processing container; introducing, into the processing container, etching gases in which a deposition-type gas composed of at least two of C, H, and F is added to etching gas selected from the group consisting of Cl2 gas, BCl3 gas, HBr gas, and the combination thereof; applying a pulse-modulated high-frequency voltage between a pair of electrodes that are provided in the processing container so as to be opposed to each other and to hold the semiconductor substrate, such that the high-frequency voltage is turned on and off to establish a duty ratio; generating a plasma between the pair of electrodes; and etching the semiconductor substrate using the plasma.
    Type: Application
    Filed: May 26, 2011
    Publication date: November 29, 2012
    Applicant: NANYA TECHNOLOGY CORPORATION
    Inventors: Chih Ching Lin, Yi Nan Chen, Hsien Wen Liu
  • Publication number: 20120302290
    Abstract: A mobile phone includes at least two subscriber identity module (SIM) cards. The mobile phone queries a number portability database (NPDB) for at least two telecom operators of the at least two SIM cards. The mobile phone queries the NPDB for a telecom operator of an outgoing number dialed using the mobile phone. The mobile phone selects one SIM card with one telecom operator same as the telecom operator of the outgoing number from the at least two SIM cards.
    Type: Application
    Filed: June 13, 2011
    Publication date: November 29, 2012
    Applicant: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: HISH-HSIEN TSAI, YI-WEN LIU
  • Publication number: 20120302030
    Abstract: A method of fabricating a deep trench capacitor includes the steps as follows. Firstly, a substrate having a trench therein is provided. Then, a bottom electrode is formed in the substrate around the trench. Later, a capacitor dielectric layer is formed to surround an inner sidewall of the trench. After that, a first conductive layer is form to fill up the trench. Subsequently, a material layer is formed on the substrate. Later, a hole is formed in the material layer, wherein the hole is directly above the trench. Finally, a second conductive layer is form to fill in the hole.
    Type: Application
    Filed: May 29, 2011
    Publication date: November 29, 2012
    Inventors: Hsiu-Chun Lee, Yi-Nan Chen, Hsien-Wen Liu
  • Publication number: 20120302062
    Abstract: A method of via formation in a semiconductor device includes the following steps of providing a photoresist with a photoresist pattern defining an opening of a via, wherein the photoresist comprising a thermally cross-linking material is disposed on a structure layer; dry-etching the structure layer to a first depth through the opening; baking the thermally cross-linking material to reduce the opening; and dry-etching the structure layer to a second depth through the reduced opening, wherein the second depth is greater than the first depth.
    Type: Application
    Filed: May 26, 2011
    Publication date: November 29, 2012
    Applicant: NANYA TECHNOLOGY CORPORATION
    Inventors: Chih Ching Lin, Yi Nan Chen, Hsien Wen Liu
  • Patent number: 8320223
    Abstract: An optical storage apparatus and a method for eliminating a write power transient thereof are provided. The method includes following steps. First, a target voltage level of a write voltage when next time the optical storage apparatus writes data is obtained. Then, a command value is updated by using the target voltage level according to a relationship between the command value and the write voltage. Next, the write voltage of the optical storage apparatus is pre-charged to the target voltage level according to the updated command value. Thereby, the write power transient of the optical storage apparatus can be eliminated.
    Type: Grant
    Filed: April 27, 2009
    Date of Patent: November 27, 2012
    Assignee: Sunplus Technology Co., Ltd.
    Inventor: Yao-Wen Liu