Abstract: A distortion correction device and method for power amplifier are provided. The power amplifier receives an input signal and generates a first output signal. The distortion correction device includes a self-mixing mixer and an adaptive calculator. The method includes steps of: utilizing the self-mixing mixer to receive the first output signal and generate a second output signal based on the first output signal, wherein the second output signal includes a plurality of baseband components corresponding to signal spectrum of the input signal; and utilizing the adaptive calculator to perform an adaptation algorithm to generate a look-up table based on the baseband components.

Abstract: An intra prediction method for a luma block of a video is provided. The present invention provides a solution for unifying the intra prediction of the luma block of the video, which simplifies a plurality of prediction equations defined by video standard. The predication values of common terms in the prediction equations are calculated in advance and directly selected for predicting the luma block of the video. Accordingly, only a few function parameters or register settings are needed to be modified, and then a plurality of prediction modes may use the same software function or hardware circuit to obtain the prediction values.

Abstract: An impedance correction device and a method thereof are provided. A step generator is used to generate a step signal and send to a circuit under test. A reflected signal returned back from the circuit under test is used as a measurement signal; and the measurement signal can be measured to obtain a characteristic impedance value. When the measurement signal is greater than the initially measured step signal, an impedance value of a correction resistor is increased; when the measurement signal is smaller than the initially measured step signal, the impedance value of the correction resistor is reduced. Through adjustment of the correction impedance value, impedance matching between the correction impedance value and the characteristic impedance value is achieved.

Abstract: A decoding method comprising the following steps is provided. The mth lookup index for a new lookup table is obtained according to the number of leading 1's in the bit stream. The nth base Huffman code in a simplified Huffman table is obtained according to the mth lookup index. The (n+1) most significant bits (MSB) are obtained from the bit stream according to the nth base Huffman code. A difference is generated according to the (n+1) MSBs in the bit stream and the nth base Huffman code. Whether the difference is less than 0 is checked. If yes, a symbol index is generated according to the difference and the nth base symbol index, and a symbol is obtained according to the symbol index. If no, n is decreased or increased by 1 according to the method being used, and the data in the simplified Huffman table is compared continually.

Abstract: According to some embodiments, context information is accessed for a current image block being processed. The context information may be, for example, associated with a block neighboring the current block, and the accessing may be performed in accordance with an address. At least one of a plurality of modular indexes may then be adjusted, and a next address may be determined in accordance with the plurality of modular indexes.

Abstract: A decoding method comprising the following steps is provided. The mth lookup index for a new lookup table is obtained according to the number of leading 1's in the bit stream. The nth base Huffman code in a simplified Huffman table is obtained according to the mth lookup index. The (n+1) most significant bits (MSB) are obtained from the bit stream according to the nth base Huffman code. A difference is generated according to the (n+1) MSBs in the bit stream and the nth base Huffman code. Whether the difference is less than 0 is checked. If yes, a symbol index is generated according to the difference and the nth base symbol index, and a symbol is obtained according to the symbol index. If no, n is decreased or increased by 1 according to the method being used, and the data in the simplified Huffman table is compared continually.

Abstract: Encoding digital video frames in intra-prediction mode by selecting reference data locations for blocks adjacent a current block identified by a writing pointer using reading pointer offsets added to the writing pointer. The reading pointer offsets include separate offsets for even and odd macro block rows of the frame that when added to the writing pointer create writing pointers to reference data for blocks located to the left, to the left and above, and above the current block. The offsets are pre-calculated and preloaded in an offset buffer, considering the number of macro blocks in a row of the frame, the number of blocks in a macro block, the number of reference data samples of a block, and the number of adjacent blocks reference data to be read. The concept can be applied to various video processing luminance components, chrominance components, and processing standards.

Abstract: A distortion correction device and method for power amplifier are provided. The power amplifier receives an input signal and generates a first output signal. The distortion correction device includes a self-mixing mixer and an adaptive calculator. The method includes steps of: utilizing the self-mixing mixer to receive the first output signal and generate a second output signal based on the first output signal, wherein the second output signal includes a plurality of baseband components corresponding to signal spectrum of the input signal; and utilizing the adaptive calculator to perform an adaptation algorithm to generate a look-up table based on the baseband components.

Abstract: A decoding method and a decoding apparatus is provided. The decoding apparatus includes a control unit, a lookup unit, an arithmetic unit, a first switch and a second switch. The control unit receives a part of a bin string. The lookup unit finds out a flag, a length and an indicator, corresponding to the part of the bin string, from a lookup table according to the part of the bin string and a node, and judges whether the flag is equal to a predetermined value. The arithmetic unit finds out a syntax element symbol corresponding to the bin string according to a basic syntax element symbol. The first switch connects the control unit to the lookup unit or the arithmetic unit. The second switch outputs the indicator as the basic syntax element symbol to the arithmetic unit or feeds the indicator as a next node back to the lookup unit.

Abstract: Encoding or decoding digital video frames in intra-prediction mode by selecting column reference data locations for blocks adjacent a current block from a column reference data buffer storing column reference data samples for no more than two macro blocks of the frame. In some cases, the column reference data buffer may include a storage size for samples of a first column of data of blocks of one macro block of luminance samples. Encoding and decoding may also include selecting row reference data locations for blocks adjacent a current block from a row reference data buffer storing row reference data samples for at least one row of macro blocks of the frame. In some cases, the row reference data buffer may include storage for samples of a first row of data of fourteen successive blocks spanning two rows. The concept can be applied to various video processing components and standards.

Abstract: Encoding or decoding digital video frames in intra-prediction mode by selecting column reference data locations for blocks adjacent a current block from a column reference data buffer storing column reference data samples for no more than two macro blocks of the frame. In some cases, the column reference data buffer may include a storage size for samples of a first column of data of blocks of one macro block of luminance samples. Encoding and decoding may also include selecting row reference data locations for blocks adjacent a current block from a row reference data buffer storing row reference data samples for at least one row of macro blocks of the frame. In some cases, the row reference data buffer may include storage for samples of a first row of data of fourteen successive blocks spanning two rows. The concept can be applied to various video processing components and standards.

Abstract: An adjusting method for reducing in-phase/quadrature-phase (I/Q) mismatch in a transmitter includes the steps of: a) receiving a first in-phase signal and a first quadrature-phase signal; b) adjusting a set of parameters such that an extent of I/Q mismatch related to the first in-phase signal and the first quadrature-phase signal is reduced; c) receiving a second in-phase signal and a second quadrature-phase signal, the second in-phase signal differing from the first in-phase signal in one of frequency and phase; d) adjusting the set of parameters such that an extent of I/Q mismatch related to the second in-phase signal and the second quadrature-phase signal is reduced; and e) determining final values for the set of parameters based on adjustment results of steps b) and d) such that extents of I/Q mismatch related to different frequencies are reduced.

Abstract: An intra prediction method for a luma block of a video is provided. The present invention provides a solution for unifying the intra prediction of the luma block of the video, which simplifies a plurality of prediction equations defined by video standard. The predication values of common terms in the prediction equations are calculated in advance and directly selected for predicting the luma block of the video. Accordingly, only a few function parameters or register settings are needed to be modified, and then a plurality of prediction modes may use the same software function or hardware circuit to obtain the prediction values.

Abstract: Arbitrary patterns of address locations of digital data can be efficiently read from a memory of a signal processor. For example, a first memory address generator receives a first memory command signal from a first communication register to retrieve a first set of data from memory according to a look up table of memory addresses. The first memory access generator reads the look up table of memory addresses, which contain a second set of memory commands and reroutes the second set of commands to a bypass register. In turn, the second set of memory commands stored at the bypass register are read by a second memory address generator which retrieves a second set of data from memory according to the second set of memory command signals read out of memory by the first memory address generator.

Abstract: According to some embodiments, bin data may be input and, based on a portion of the bin data, an entry in a search table may be determined. An indication of whether the search is complete may then be read from the search table along with at least one of: (i) a base symbol value or (ii) information about a next node. If the search is not complete, the process may continue to determine entries in the search table based on the information about the next node and additional portions of the bin data. When the search is complete, a decoded symbol may be calculated based on the last base symbol value and a remaining portion of the bin data associated with an extra bin length read from the search table.

Abstract: Arbitrary patterns of address locations of digital data can be efficiently read from a memory of a signal processor. For example, a first memory address generator receives a first memory command signal from a first communication register to retrieve a first set of data from memory according to a look up table of memory addresses. The first memory access generator reads the look up table of memory addresses, which contain a second set of memory commands and reroutes the second set of commands to a bypass register. In turn, the second set of memory commands stored at the bypass register are read by a second memory address generator which retrieves a second set of data from memory according to the second set of memory command signals read out of memory by the first memory address generator.

Abstract: Arbitrary patterns of address locations of digital data can be efficiently read from a memory of a signal processor. For example, a first memory address generator receives a first memory command signal from a first communication register to retrieve a first set of data from memory according to a look up table of memory addresses. The first memory access generator reads the look up table of memory addresses, which contain a second set of memory commands and reroutes the second set of commands to a bypass register. In turn, the second set of memory commands stored at the bypass register are read by a second memory address generator which retrieves a second set of data from memory according to the second set of memory command signals read out of memory by the first memory address generator.

Abstract: According to some embodiments, context information is accessed for a current image block being processed. The context information may be, for example, associated with a block neighboring the current block, and the accessing may be performed in accordance with an address. At least one of a plurality of modular indexes may then be adjusted, and a next address may be determined in accordance with the plurality of modular indexes.

Abstract: Encoding or decoding digital video frames in intra-prediction mode by selecting column reference data locations for blocks adjacent a current block from a column reference data buffer storing column reference data samples for no more than two macro blocks of the frame. In some cases, the column reference data buffer may include a storage size for samples of a first column of data of blocks of one macro block of luminance samples. Encoding and decoding may also include selecting row reference data locations for blocks adjacent a current block from a row reference data buffer storing row reference data samples for at least one row of macro blocks of the frame. In some cases, the row reference data buffer may include storage for samples of a first row of data of fourteen successive blocks spanning two rows. The concept can be applied to various video processing components and standards.

Abstract: An address generator is provided with an input to receive a base address for an array of storage locations, an offset generator to generate a number of offsets, and a combiner coupled to the input and the offset generator to combine the base address with the offsets to generate a number of access addresses for accessing the array of storage locations in accordance with a deterministic access pattern having at least one non-sequential access. In various embodiments, the address generator is included in each of a number of signal processing units, which in turn are included in a digital media processor.