Abstract: According to some embodiments, context information is accessed for a current image block being processed. The context information may be, for example, associated with a block neighboring the current block, and the accessing may be performed in accordance with an address. At least one of a plurality of modular indexes may then be adjusted, and a next address may be determined in accordance with the plurality of modular indexes.

Abstract: Encoding or decoding digital video frames in intra-prediction mode by selecting column reference data locations for blocks adjacent a current block from a column reference data buffer storing column reference data samples for no more than two macro blocks of the frame. In some cases, the column reference data buffer may include a storage size for samples of a first column of data of blocks of one macro block of luminance samples. Encoding and decoding may also include selecting row reference data locations for blocks adjacent a current block from a row reference data buffer storing row reference data samples for at least one row of macro blocks of the frame. In some cases, the row reference data buffer may include storage for samples of a first row of data of fourteen successive blocks spanning two rows. The concept can be applied to various video processing components and standards.

Abstract: An address generator is provided with an input to receive a base address for an array of storage locations, an offset generator to generate a number of offsets, and a combiner coupled to the input and the offset generator to combine the base address with the offsets to generate a number of access addresses for accessing the array of storage locations in accordance with a deterministic access pattern having at least one non-sequential access. In various embodiments, the address generator is included in each of a number of signal processing units, which in turn are included in a digital media processor.

Abstract: An embodiment includes a method that includes receiving a number of pixels of video data. The method also includes commencing a first arithmetic operation of a matrix of the number of pixels with a transpose of a constant matrix prior to a first element of the second row being received.

Abstract: Encoding digital video frames in intra-prediction mode by selecting reference data locations for blocks adjacent a current block identified by a writing pointer using reading pointer offsets added to the writing pointer. The reading pointer offsets include separate offsets for even and odd macro block rows of the frame that when added to the writing pointer create writing pointers to reference data for blocks located to the left, to the left and above, and above the current block. The offsets are pre-calculated and preloaded in an offset buffer, considering the number of macro blocks in a row of the frame, the number of blocks in a macro block, the number of reference data samples of a block, and the number of adjacent blocks reference data to be read. The concept can be applied to various video processing luminance components, chrominance components, and processing standards.

Abstract: Various methods, apparatuses, and systems are described to determine motion estimation. An image processing engine may have a full search motion estimation engine that matches blocks of pixel data from a first video frame to a second video frame in a raster order to determine the motion estimation. The image processing engine may further include a post processing stage to implement a search pattern algorithm on blocks of pixel data in a search window, where the search pattern starts and proceeds outward from a central region of the search window.

Abstract: Implementations of a progressive two-dimensional pyramid filter bank are disclosed including a method of adding a first and a last input signal sample to a sum of input samples of a next lower-tap filter of a current filter to produce a sum of input signal samples for the current filter; and adding the sum of input signal samples for the current filter to an output signal sample of the next lower-tap filter of the current filter to produce an output signal sample for the current filter. In one implementation the first and second adding is performed by different adders. In another implementation the first and second adding is applied by column and by row.

Abstract: An address generator is provided with an input to receive a base address for an array of storage locations, an offset generator to generate a number of offsets, and a combiner coupled to the input and the offset generator to combine the base address with the offsets to generate a number of access addresses for accessing the array of storage locations in accordance with a deterministic access pattern having at least one non-sequential access. In various embodiments, the address generator is included in each of a number of signal processing units, which in turn are included in a digital media processor.

Abstract: Arbitrary patterns of address locations of digital data can be efficiently read from a memory of a signal processor. For example, a first memory address generator receives a first memory command signal from a first communication register to retrieve a first set of data from memory according to a look up table of memory addresses. The first memory access generator reads the look up table of memory addresses, which contain a second set of memory commands and reroutes the second set of commands to a bypass register. In turn, the second set of memory commands stored at the bypass register are read by a second memory address generator which retrieves a second set of data from memory according to the second set of memory command signals read out of memory by the first memory address generator.

Abstract: Numerous embodiments for a method of performing Huffman decoding are disclosed.

Abstract: Embodiments of a progressive 2D pyramid filter bank are disclosed.

Abstract: Numerous embodiments for a method of performing Huffman decoding are disclosed.