Abstract: A semiconductor device includes a plurality of transistors, a plurality of metal layers, and a resistor. The plurality of transistors are connected in series between a power terminal and a ground terminal, and gate terminals of the transistors being connected together. The plurality of metal layers are overlaid above the plurality of transistors. The resistor is implemented between two of the plurality of metal layers.

Abstract: In certain embodiments, the present disclosure provides compounds and methods of increasing the amount or activity of a target protein in a cell. In certain embodiments, the compounds comprise a translation suppression element inhibitor. In certain embodiments, the translation suppression element inhibitor is a uORF inhibitor. In certain embodiments, the uORF inhibitor is an antisense compound.

Abstract: Methods of designing integrated circuits incorporating an analog ECO flow are provided. An example method comprises receiving an initial design and performing an auto-marker process. The auto-marker process comprises performing a first auto-marker process to surround a first plurality of active cells of the design with first computer-aided design (CAD) layers corresponding to a first plurality of engineering change order (ECO) cells, performing an enhanced auto-marker process to cover irregular shapes of the design with second CAD layers corresponding to a second plurality of ECO cells, and performing a second auto-marker process to fill empty areas of the design with third CAD layers corresponding to a third plurality of ECO cells. The method further includes filling the design with the first plurality of ECO cells, the second plurality of ECO cells, and the third plurality of ECO cells.

Abstract: A method of manufacturing a semiconductor device includes forming M_1st segments in a first metallization layer including: forming first and second M_1st segments for which corresponding long axes extend in a first direction and are substantially collinear, the first and second M_1st segments being free from another instance of M_1st segment being between the first and second M_1st segments; and (A) where the first and second M_1st segments are designated for corresponding voltage values having a difference equal to or less than a reference value, separating the first and second M_1st segments by a first gap; or (B) where the first and second M_1st segments are designated for corresponding voltage values having a difference greater than the reference value, separating the first and second M_1st segments by a second gap, a second size of the second gap being greater than a first size of the first gap.

Abstract: An IC device includes a transistor including a gate structure between first and second active areas, a first S/D metal portion overlying the first active area, and a second S/D metal portion overlying the second active area. A load resistor including a third S/D metal portion is positioned on a dielectric layer and in a same layer as the first and second S/D metal portions. A first via overlies the first S/D metal portion, second and third vias overlie the third S/D metal portion, and a first conductive structure is configured to electrically connect the first via to the second via.

Abstract: The present disclosure provides a method of making a semiconductor device. The method includes forming a semiconductor stack on a substrate, wherein the semiconductor stack includes first semiconductor layers of a first semiconductor material and second semiconductor layers of a second semiconductor material alternatively stacked on the substrate; patterning the semiconductor stack and the substrate to form a trench and an active region being adjacent the trench; epitaxially growing a liner of the first semiconductor material on sidewalls of the trench and sidewalls of the active region; forming an isolation feature in the trench; performing a rapid thermal nitridation process, thereby converting the liner into a silicon nitride layer; and forming a cladding layer of the second semiconductor material over the silicon nitride layer.

Abstract: The present disclosure provides oligomeric compound comprising a modified oligonucleotide having a central region comprising one or more modifications. In certain embodiments, the present disclosure provides oligomeric compounds having an improved therapeutic index or an increased maximum tolerated dose.

Abstract: A sensor for detecting a target analyte in a sample includes a pair of conducting electrodes that are separated by a gap. An insulator is disposed in the gap between the electrodes. Plural wells are defined by one of the electrodes and the insulator, to expose the other of the electrodes. The wells are configured to receive a sample including a target analyte. The target analyte, when present in the sample received in the wells, modulates an impedance between the electrodes. The modulated impedance, which is measurable with an applied electrical voltage, is indicative of the concentration of the target analyte in the sample. The wells can include antibodies immobilized inside the wells, to bind the target analyte, which can be a cytokine. Also provided are a method for label-free sensing of a target analyte in a sample, and a transcutaneous impedance sensor for label-free, in-situ biomarker detection.

Abstract: Systems, methods, and devices are disclosed herein for developing a cell design. Operations of a plurality of electrical cells are simulated to collect a plurality of electrical parameters. A machine learning model is trained using the plurality of electrical parameters. The trained machine learning model receives data having cell layout design constraints. The trained machine learning model determines a cell layout for the received data based on the plurality of electrical parameters. The cell layout is provided for further characterization of electrical performance within the cell layout design constraints.

Abstract: Techniques for generating one or more non-final layouts for an analog integrated circuit are disclosed. The techniques include generating a non-final layout of an analog integrated circuit based on device specifications, partitioning the non-final layout into a plurality of subcells, merging the verified sub-cells to form a merged layout of the analog integrated circuit, and performing quality control checks on the merged layout. Additionally or alternatively, generating the non-final layout can include determining an allowable spacing between adjacent cells of different cell types or inserting one or more filler cells into a filler zone in the non-final layout.

Abstract: A method of generating a layout design of an integrated circuit includes forming an active zone and partitioning the active zone into a center portion between a first side portion and a second side portion. The method also includes forming a plurality of gate-strips and forming a routing line. The plurality of gate-strips includes a first group of gate-strips intersecting the active zone over first channel regions in the center portion, a second group of gate-strips intersecting the active zone over second channel regions in the center portion, a third group of gate-strips intersecting the active zone over third channel regions in the first side portion, and a fourth group of gate-strips intersecting the active zone over fourth channel regions in the second side portion.

Abstract: Techniques for generating one or more non-final layouts for an analog integrated circuit are disclosed. The techniques include generating a non-final layout of an analog integrated circuit based on device specifications, partitioning the non-final layout into a plurality of subcells, merging the verified sub-cells to form a merged layout of the analog integrated circuit, and performing quality control checks on the merged layout. Additionally or alternatively, generating the non-final layout can include determining an allowable spacing between adjacent cells of different cell types or inserting one or more filler cells into a filler zone in the non-final layout.

Abstract: Systems, methods, and devices are disclosed herein for developing a cell design. Operations of a plurality of electrical cells are simulated to collect a plurality of electrical parameters. A machine learning model is trained using the plurality of electrical parameters. The trained machine learning model receives data having cell layout design constraints. The trained machine learning model determines a cell layout for the received data based on the plurality of electrical parameters. The cell layout is provided for further characterization of electrical performance within the cell layout design constraints.

Abstract: A semiconductor device including a first active region having a first active configuration, a second active region having a second, and different, active configuration, and a transition cell arranged between the first and second active regions in which the transition cell has a transitional configuration that is different from and compatible with both the first active configuration and the second active configuration.

Abstract: A semiconductor device includes a first semiconductor well. The semiconductor device includes a channel structure disposed above the first semiconductor well and extending along a first lateral direction. The semiconductor device includes a gate structure extending along a second lateral direction and straddling the channel structure. The semiconductor device includes a first epitaxial structure disposed on a first side of the channel structure. The semiconductor device includes a second epitaxial structure disposed on a second side of the channel structure, the first side and second side opposite to each other in the first lateral direction. The first epitaxial structure is electrically coupled to the first semiconductor well with a second semiconductor well in the first semiconductor well, and the second epitaxial structure is electrically isolated from the first semiconductor well with a dielectric layer.

Abstract: Various techniques are disclosed for automatically generating sub-cells for a non-final layout of an analog integrated circuit. Device specifications and partition information for the analog integrated circuit is received. Based on the device specifications and the partition information, first cut locations for a first set of cuts to be made along a first direction of a non-final layout of the analog integrated circuit and second cut locations for a second set of cuts to be made along a second direction in the non-final layout are determined. The first set of cuts are made in the non-final layout at the cut locations to produce a temporary layout. The second set of cuts are made in the temporary layout at the cut locations to produce a plurality of sub-cells.

Abstract: A semiconductor device including a first active region having a first active configuration, a second active region having a second, and different, active configuration, and a transition cell arranged between the first and second active regions in which the transition cell has a transitional configuration that is different from and compatible with both the first active configuration and the second active configuration.

Abstract: The method in embodiments of this application includes: obtaining a plurality of types of data, where all of the plurality of types of data have different sources and different data types; performing knowledge extraction on the plurality of types of data to obtain a knowledge graph, where the knowledge graph includes a plurality of knowledge entities and an association relationship between the plurality of knowledge entities, and the plurality of knowledge entities include different data types; and performing knowledge representation on each knowledge entity by using a knowledge representation algorithm corresponding to a data type of each knowledge entity, and initializing a weight of the relationship between the plurality of knowledge entities in the knowledge graph, to obtain a vector graph, where the vector graph is used to train an artificial intelligence AI task model.

Abstract: A sensor for detecting a target analyte in a sample includes a pair of conducting electrodes that are separated by a gap. An insulator is disposed in the gap between the electrodes. Plural wells are defined by one of the electrodes and the insulator, to expose the other of the electrodes. The wells are configured to receive a sample including a target analyte. The target analyte, when present in the sample received in the wells, modulates an impedance between the electrodes. The modulated impedance, which is measurable with an applied electrical voltage, is indicative of the concentration of the target analyte in the sample. The wells can include antibodies immobilized inside the wells, to bind the target analyte, which can be a cytokine. Also provided are a method for label-free sensing of a target analyte in a sample, and a transcutaneous impedance sensor for label-free, in-situ biomarker detection.