Patents by Inventor Wen Shen
Wen Shen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250238587Abstract: Systems and methods are provided for designing an integrated circuit device. In one example, a method for designing an integrated circuit device may include the operations of: receiving a schematic diagram of the integrated circuit device; generating, by a simulation program, a first transient simulation of the integrated circuit device based on the schematic diagram; determining from the first transient simulation of the integrated circuit device a plurality of maximum voltage change values between conductor networks (nets) within the schematic diagram of the integrated circuit device; storing the plurality of maximum voltage change values for the schematic diagram of the integrated circuit device in a computer readable medium; and utilizing, by a layout program, the stored plurality of maximum voltage change values to generate a layout design for the integrated circuit device according to one or more high voltage design constraints.Type: ApplicationFiled: April 11, 2025Publication date: July 24, 2025Inventors: Shenggao Li, Szu-Chun Tsao, Wen-Shen Chou
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Publication number: 20250228010Abstract: A method for fabricating integrated circuits comprises: forming, on a frontside of a substrate, a plurality of active components of an integrated circuit; forming, on the frontside of the substrate, a plurality of dummy components each laterally disposed next to one or more of the active components; forming a plurality of first via structures vertically extending through the substate from its backside to the frontside; forming a second via structure vertically extending through the substate from the backside to the frontside; and forming, on the backside of the substrate, a second interconnect structure.Type: ApplicationFiled: January 5, 2024Publication date: July 10, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Cheng Syu, Yu-Tao Yang, Wen-Shen Chou
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Patent number: 12356669Abstract: In a method of manufacturing a semiconductor device, a fin structure including a stacked layer of first and second semiconductor layers and a hard mask layer over the stacked layer is formed. A sacrificial cladding layer is formed over at least sidewalls of the exposed hard mask layer and stacked layer. An etching is performed to remove lateral portions of the sacrificial cladding layer, thereby leaving the sacrificial cladding layer on sidewalls of the exposed hard mask layer and stacked layer. A first dielectric layer and a second dielectric layer made of a different material than the first dielectric layer are formed. The second dielectric layer is recessed, and a third dielectric layer made of a different material than the second dielectric layer is formed on the recessed second dielectric layer. During the etching operation, a protection layer is formed over the sacrificial cladding layer.Type: GrantFiled: April 30, 2024Date of Patent: July 8, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shu-Wen Shen, Chen-Ping Chen
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Publication number: 20250217567Abstract: A semiconductor device includes a digital section, an analog active section, and an analog guard ring section between the analog active section and the digital section. The semiconductor device includes M_1st segments. The M_1st segments include a first M_1st segment extending in a first direction; and a second M_1st segment extending in the first direction, wherein the second M_1st segment is collinear with the first M_1st segment, and a first gap is between the first M_1st segment and the second M_1st segment. The semiconductor device includes active regions in a substrate. The active regions include first and second active regions extending in the first direction, the first active region being adjacent to the second active region, and the first and second active regions are separated by a second gap greater than or equal to the first gap.Type: ApplicationFiled: March 18, 2025Publication date: July 3, 2025Inventors: Ming-Cheng SYU, Po-Zeng KANG, Yung-Hsu CHUANG, Shu-Chin TAI, Wen-Shen CHOU, Yung-Chow PENG
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Patent number: 12349469Abstract: In an integrated circuit, the gates of a first high-threshold transistor and a first low-threshold transistor are connected together, and the gates of a second high-threshold transistor and a second low-threshold transistor are connected together. The drain of the first high-threshold transistor is conductively connected to the source of the first low-threshold transistor, and the drain of the second high-threshold transistor is conductively connected to the source of the second low-threshold transistor. The gates of the first low-threshold transistor and the second low-threshold transistor are conductively connected to the drain of the first low-threshold transistor. The threshold-voltage of the first high-threshold transistor is larger than a threshold-voltage of the first low-threshold transistor. The threshold-voltage of the second high-threshold transistor is larger than a threshold-voltage of the second low-threshold transistor.Type: GrantFiled: November 22, 2023Date of Patent: July 1, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Tao Yang, Wen-Shen Chou, Yung-Chow Peng
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Patent number: 12339174Abstract: A semiconductor device includes a plurality of active area structures extending in parallel, first and second dummy gate layers spanning the plurality of active area structures, a first active device including first portions of the plurality of active area structures between the first and second dummy gate layers, a metal layer spanning the plurality of active area structures between the first and second dummy gate layers, and a pair of vias positioned at opposite ends of the metal layer. A first via of the pair of vias is configured to be electrically connected to ground, and a second via of the pair of vias is configured to be electrically connected to a current source and a circuit configured to measure a voltage at the node.Type: GrantFiled: January 24, 2024Date of Patent: June 24, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Po-Zeng Kang, Wen-Shen Chou, Yung-Chow Peng
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Patent number: 12328519Abstract: An image sensor, including a photosensitive pixel array, a storage element, and a displacement processing element, is provided. The photosensitive pixel array includes a photosensitive pixel. The storage element is configured to store a first sensing result of the photosensitive pixel at a first time point. The displacement processing element is coupled to the storage element to receive the first sensing result. The displacement processing element is configured to generate displacement information, wherein an image frame with the displacement information is transmitted to the outside of the image sensor.Type: GrantFiled: February 15, 2022Date of Patent: June 10, 2025Assignee: Novatek Microelectronics Corp.Inventors: Wen-Shen Wuen, Shen-Fu Tsai, Cho-Hsuan Jhang
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Patent number: 12299370Abstract: Systems and methods are provided for designing an integrated circuit device. In one example, a method for designing an integrated circuit device may include the operations of: receiving a schematic diagram of the integrated circuit device; generating, by a simulation program, a first transient simulation of the integrated circuit device based on the schematic diagram; determining from the first transient simulation of the integrated circuit device a plurality of maximum voltage change values between conductor networks (nets) within the schematic diagram of the integrated circuit device; storing the plurality of maximum voltage change values for the schematic diagram of the integrated circuit device in a computer readable medium; and utilizing, by a layout program, the stored plurality of maximum voltage change values to generate a layout design for the integrated circuit device according to one or more high voltage design constraints.Type: GrantFiled: March 8, 2022Date of Patent: May 13, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shenggao Li, Szu-Chun Tsao, Wen-Shen Chou
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Patent number: 12272640Abstract: A semiconductor device includes a plurality of transistors, a plurality of metal layers, and a resistor. The plurality of transistors are connected in series between a power terminal and a ground terminal, and gate terminals of the transistors being connected together. The plurality of metal layers are overlaid above the plurality of transistors. The resistor is implemented between two of the plurality of metal layers.Type: GrantFiled: April 20, 2023Date of Patent: April 8, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Po-Zeng Kang, Wen-Shen Chou, Yung-Chow Peng
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Publication number: 20250109164Abstract: In certain embodiments, the present disclosure provides compounds and methods of increasing the amount or activity of a target protein in a cell. In certain embodiments, the compounds comprise a translation suppression element inhibitor. In certain embodiments, the translation suppression element inhibitor is a uORF inhibitor. In certain embodiments, the uORF inhibitor is an antisense compound.Type: ApplicationFiled: May 20, 2024Publication date: April 3, 2025Applicant: Ionis Pharmaceuticals, Inc.Inventors: Stanley T. Crooke, Xue-hai Liang, Wen Shen
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Publication number: 20250094682Abstract: Methods of designing integrated circuits incorporating an analog ECO flow are provided. An example method comprises receiving an initial design and performing an auto-marker process. The auto-marker process comprises performing a first auto-marker process to surround a first plurality of active cells of the design with first computer-aided design (CAD) layers corresponding to a first plurality of engineering change order (ECO) cells, performing an enhanced auto-marker process to cover irregular shapes of the design with second CAD layers corresponding to a second plurality of ECO cells, and performing a second auto-marker process to fill empty areas of the design with third CAD layers corresponding to a third plurality of ECO cells. The method further includes filling the design with the first plurality of ECO cells, the second plurality of ECO cells, and the third plurality of ECO cells.Type: ApplicationFiled: September 20, 2023Publication date: March 20, 2025Inventors: Ayushi Agrawal, Yu-Tao Yang, Ming-Cheng Syu, Wen-Shen Chou, Yung-Chow Peng
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Patent number: 12254257Abstract: A method of manufacturing a semiconductor device includes forming M_1st segments in a first metallization layer including: forming first and second M_1st segments for which corresponding long axes extend in a first direction and are substantially collinear, the first and second M_1st segments being free from another instance of M_1st segment being between the first and second M_1st segments; and (A) where the first and second M_1st segments are designated for corresponding voltage values having a difference equal to or less than a reference value, separating the first and second M_1st segments by a first gap; or (B) where the first and second M_1st segments are designated for corresponding voltage values having a difference greater than the reference value, separating the first and second M_1st segments by a second gap, a second size of the second gap being greater than a first size of the first gap.Type: GrantFiled: January 21, 2022Date of Patent: March 18, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ming-Cheng Syu, Po-Zeng Kang, Yung-Hsu Chuang, Shu-Chin Tai, Wen-Shen Chou, Yung-Chow Peng
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Patent number: 12249601Abstract: An IC device includes a transistor including a gate structure between first and second active areas, a first S/D metal portion overlying the first active area, and a second S/D metal portion overlying the second active area. A load resistor including a third S/D metal portion is positioned on a dielectric layer and in a same layer as the first and second S/D metal portions. A first via overlies the first S/D metal portion, second and third vias overlie the third S/D metal portion, and a first conductive structure is configured to electrically connect the first via to the second via.Type: GrantFiled: July 29, 2020Date of Patent: March 11, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Po-Zeng Kang, Wen-Shen Chou, Yung-Chow Peng
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Patent number: 12249539Abstract: The present disclosure provides a method of making a semiconductor device. The method includes forming a semiconductor stack on a substrate, wherein the semiconductor stack includes first semiconductor layers of a first semiconductor material and second semiconductor layers of a second semiconductor material alternatively stacked on the substrate; patterning the semiconductor stack and the substrate to form a trench and an active region being adjacent the trench; epitaxially growing a liner of the first semiconductor material on sidewalls of the trench and sidewalls of the active region; forming an isolation feature in the trench; performing a rapid thermal nitridation process, thereby converting the liner into a silicon nitride layer; and forming a cladding layer of the second semiconductor material over the silicon nitride layer.Type: GrantFiled: June 7, 2022Date of Patent: March 11, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shu-Wen Shen, Jiun-Ming Kuo, Yuan-Ching Peng, Ji-Xuan Yang, Jheng-Wei Lin, Chien-Hung Chen
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Patent number: 12234447Abstract: The present disclosure provides oligomeric compound comprising a modified oligonucleotide having a central region comprising one or more modifications. In certain embodiments, the present disclosure provides oligomeric compounds having an improved therapeutic index or an increased maximum tolerated dose.Type: GrantFiled: March 17, 2022Date of Patent: February 25, 2025Assignee: Ionis Pharmaceuticals, Inc.Inventors: Punit P. Seth, Michael Oestergaard, Michael T. Migawa, Xue-Hai Liang, Wen Shen, Stanley T. Crooke, Eric E. Swayze
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Publication number: 20250045503Abstract: Systems, methods, and devices are disclosed herein for developing a cell design. Operations of a plurality of electrical cells are simulated to collect a plurality of electrical parameters. A machine learning model is trained using the plurality of electrical parameters. The trained machine learning model receives data having cell layout design constraints. The trained machine learning model determines a cell layout for the received data based on the plurality of electrical parameters. The cell layout is provided for further characterization of electrical performance within the cell layout design constraints.Type: ApplicationFiled: October 18, 2024Publication date: February 6, 2025Inventors: Wen-Shen Chou, Jie-Ren Huang, Yu-Tao Yang, Yung-Chow Peng, Yung-Hsu Chuang
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Publication number: 20250041866Abstract: A sensor for detecting a target analyte in a sample includes a pair of conducting electrodes that are separated by a gap. An insulator is disposed in the gap between the electrodes. Plural wells are defined by one of the electrodes and the insulator, to expose the other of the electrodes. The wells are configured to receive a sample including a target analyte. The target analyte, when present in the sample received in the wells, modulates an impedance between the electrodes. The modulated impedance, which is measurable with an applied electrical voltage, is indicative of the concentration of the target analyte in the sample. The wells can include antibodies immobilized inside the wells, to bind the target analyte, which can be a cytokine. Also provided are a method for label-free sensing of a target analyte in a sample, and a transcutaneous impedance sensor for label-free, in-situ biomarker detection.Type: ApplicationFiled: August 21, 2024Publication date: February 6, 2025Inventors: Pengfei Xie, Mehdi Javanmard, Mark George Allen, Wen Shen, Naixin Song
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Publication number: 20250021737Abstract: Techniques for generating one or more non-final layouts for an analog integrated circuit are disclosed. The techniques include generating a non-final layout of an analog integrated circuit based on device specifications, partitioning the non-final layout into a plurality of subcells, merging the verified sub-cells to form a merged layout of the analog integrated circuit, and performing quality control checks on the merged layout. Additionally or alternatively, generating the non-final layout can include determining an allowable spacing between adjacent cells of different cell types or inserting one or more filler cells into a filler zone in the non-final layout.Type: ApplicationFiled: July 30, 2024Publication date: January 16, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Tao Yang, Wen-Shen Chou, Yung-Chow Peng, Yung-Hsu Chuang
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Patent number: 12199086Abstract: A method of generating a layout design of an integrated circuit includes forming an active zone and partitioning the active zone into a center portion between a first side portion and a second side portion. The method also includes forming a plurality of gate-strips and forming a routing line. The plurality of gate-strips includes a first group of gate-strips intersecting the active zone over first channel regions in the center portion, a second group of gate-strips intersecting the active zone over second channel regions in the center portion, a third group of gate-strips intersecting the active zone over third channel regions in the first side portion, and a fourth group of gate-strips intersecting the active zone over fourth channel regions in the second side portion.Type: GrantFiled: April 18, 2022Date of Patent: January 14, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Tao Yang, Wen-Shen Chou, Yung-Chow Peng
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Patent number: D1062910Type: GrantFiled: June 30, 2022Date of Patent: February 18, 2025Inventor: Wen Shen