Patents by Inventor Wen Shen

Wen Shen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11704470
    Abstract: Systems, methods, and devices are disclosed herein for developing a cell design. Operations of a plurality of electrical cells are simulated to collect a plurality of electrical parameters. A machine learning model is trained using the plurality of electrical parameters. The trained machine learning model receives data having cell layout design constraints. The trained machine learning model determines a cell layout for the received data based on the plurality of electrical parameters. The cell layout is provided for further characterization of electrical performance within the cell layout design constraints.
    Type: Grant
    Filed: July 26, 2021
    Date of Patent: July 18, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Wen-Shen Chou, Jie-Ren Huang, Yu-Tao Yang, Yung-Chow Peng, Yung-Hsu Chuang
  • Publication number: 20230215933
    Abstract: In a method of manufacturing a semiconductor device, a fin structure including a stacked layer of first and second semiconductor layers and a hard mask layer over the stacked layer is formed. A sacrificial cladding layer is formed over at least sidewalls of the exposed hard mask layer and stacked layer. An etching is performed to remove lateral portions of the sacrificial cladding layer, thereby leaving the sacrificial cladding layer on sidewalls of the exposed hard mask layer and stacked layer. A first dielectric layer and a second dielectric layer made of a different material than the first dielectric layer are formed. The second dielectric layer is recessed, and a third dielectric layer made of a different material than the second dielectric layer is formed on the recessed second dielectric layer. During the etching operation, a protection layer is formed over the sacrificial cladding layer.
    Type: Application
    Filed: March 13, 2023
    Publication date: July 6, 2023
    Inventors: Shu-Wen SHEN, Chen-Ping CHEN
  • Patent number: 11684463
    Abstract: A method of repairing an oral defect model includes performing a three-dimensional oral defect model obtaining step, a defect cutting line detecting step, a defect point selecting step and a smoothing step. The three-dimensional oral defect model obtaining step is performed to scan an oral cavity to obtain a three-dimensional oral defect model message. The defect cutting line detecting step is performed to detect a defect cutting line of the three-dimension oral defect model message, and drive a displayer to display the defect cutting line. The defect point selecting step is performed to select at least one defect feature point of the defect cutting line via the displayer. The smoothing step is performed to perform a smoothing process at the at least one defect feature point, and convert the three-dimensional oral defect model message into a three-dimensional oral repaired model message to smooth the defect cutting line.
    Type: Grant
    Filed: January 12, 2021
    Date of Patent: June 27, 2023
    Assignee: China Medical University
    Inventors: Yen-Wen Shen, Lih-Jyh Fuh, Chi-Hsiung Yu
  • Publication number: 20230178418
    Abstract: The present disclosure provides a method of making a semiconductor device. The method includes forming a semiconductor stack on a substrate, wherein the semiconductor stack includes first semiconductor layers of a first semiconductor material and second semiconductor layers of a second semiconductor material alternatively stacked on the substrate; patterning the semiconductor stack and the substrate to form a trench and an active region being adjacent the trench; epitaxially growing a liner of the first semiconductor material on sidewalls of the trench and sidewalls of the active region; forming an isolation feature in the trench; performing a rapid thermal nitridation process, thereby converting the liner into a silicon nitride layer; and forming a cladding layer of the second semiconductor material over the silicon nitride layer.
    Type: Application
    Filed: June 7, 2022
    Publication date: June 8, 2023
    Inventors: Shu-Wen SHEN, Jiun-Ming KUO, Yuan-Ching PENG, Ji-Xuan YANG, Jheng-Wei LIN, Chien-Hung CHEN
  • Patent number: 11670586
    Abstract: A semiconductor device includes transistors and a resistor. The transistors are connected in series between a power terminal and a ground terminal, and gate terminals of the transistors being connected together. The resistor is overlaid above the transistors. The resistor is connected between a source terminal of the transistors and the ground terminal.
    Type: Grant
    Filed: January 3, 2022
    Date of Patent: June 6, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Po-Zeng Kang, Wen-Shen Chou, Yung-Chow Peng
  • Patent number: 11658675
    Abstract: A successive-approximation register analog-to-digital converter (SAR ADC), a correction method and a correction system are provided. The SAR ADC generates an original weight value sequence according to multiple original weight values. The SAR ADC converts an analog time-varying signal to establish a transforming curve corresponding to the original weight values. In addition, the SAR ADC generates an offset value sequence according to an offset of the transforming curve, uses the offset value sequence to correct the original weight value sequence to generate a corrected weight value sequence, and uses multiple corrected weight values of the corrected weight sequence to improve linearity of the transforming curve.
    Type: Grant
    Filed: November 22, 2021
    Date of Patent: May 23, 2023
    Assignee: Chung Yuan Christian University
    Inventors: Shih-Lun Chen, Chun Kuan Wu, Chun Yu Lin, Wen-Shen Lo
  • Publication number: 20230120087
    Abstract: According to the present disclosure, an oral rehabilitation device includes an air bladder and a pumping member. The air bladder includes a cheek-side membrane and a teeth-side membrane, and the cheek-side membrane and the teeth-side membrane are arranged opposite to each other. The pumping member is communicated with the air bladder, and the pumping member is configured for inflating the air bladder. The cheek-side membrane and the teeth-side membrane extend toward the outside of the air bladder when the pumping member is inflating the air bladder, and an extension of the cheek-side membrane is larger than an extension of the teeth-side membrane.
    Type: Application
    Filed: January 26, 2022
    Publication date: April 20, 2023
    Applicant: China Medical University
    Inventors: Lih-Jyh Fuh, Yen-Wen Shen
  • Publication number: 20230108759
    Abstract: A successive-approximation register analog-to-digital converter (SAR ADC), a correction method and a correction system are provided. The SAR ADC generates an original weight value sequence according to multiple original weight values. The SAR ADC converts an analog time-varying signal to establish a transforming curve corresponding to the original weight values. In addition, the SAR ADC generates an offset value sequence according to an offset of the transforming curve, uses the offset value sequence to correct the original weight value sequence to generate a corrected weight value sequence, and uses multiple corrected weight values of the corrected weight sequence to improve linearity of the transforming curve.
    Type: Application
    Filed: November 22, 2021
    Publication date: April 6, 2023
    Applicant: Chung Yuan Christian University
    Inventors: Shih-Lun Chen, Chun Kuan Wu, Chun Yu Lin, Wen-Shen Lo
  • Patent number: 11617918
    Abstract: According to the present disclosure, an oral rehabilitation device includes an air bladder and a pumping member. The air bladder includes a cheek-side membrane and a teeth-side membrane, and the cheek-side membrane and the teeth-side membrane are arranged opposite to each other. The pumping member is communicated with the air bladder, and the pumping member is configured for inflating the air bladder. The cheek-side membrane and the teeth-side membrane extend toward the outside of the air bladder when the pumping member is inflating the air bladder, and an extension of the cheek-side membrane is larger than an extension of the teeth-side membrane.
    Type: Grant
    Filed: January 26, 2022
    Date of Patent: April 4, 2023
    Assignee: China Medical University
    Inventors: Lih-Jyh Fuh, Yen-Wen Shen
  • Publication number: 20230095479
    Abstract: A semiconductor device structure is provided. The device includes a plurality of semiconductor layers and a gate electrode layer surrounding each semiconductor layer of the plurality of semiconductor layers. The gate electrode layer includes a first part, and a second part below the first part, the second part comprises a first portion, wherein an exterior surface of the first portion has a first radius of curvature, and a second portion below the first portion, and a third portion below the second portion, wherein an exterior surface of the third portion having a second radius of curvature different than the first radius of curvature.
    Type: Application
    Filed: November 23, 2022
    Publication date: March 30, 2023
    Inventor: Shu-Wen SHEN
  • Patent number: 11605727
    Abstract: In a method of manufacturing a semiconductor device, a fin structure including a stacked layer of first and second semiconductor layers and a hard mask layer over the stacked layer is formed. A sacrificial cladding layer is formed over at least sidewalls of the exposed hard mask layer and stacked layer. An etching is performed to remove lateral portions of the sacrificial cladding layer, thereby leaving the sacrificial cladding layer on sidewalls of the exposed hard mask layer and stacked layer. A first dielectric layer and a second dielectric layer made of a different material than the first dielectric layer are formed. The second dielectric layer is recessed, and a third dielectric layer made of a different material than the second dielectric layer is formed on the recessed second dielectric layer. During the etching operation, a protection layer is formed over the sacrificial cladding layer.
    Type: Grant
    Filed: July 6, 2021
    Date of Patent: March 14, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shu-Wen Shen, Chen-Ping Chen
  • Publication number: 20230067804
    Abstract: A plurality of first semiconductor layers and second semiconductor layers are formed over a front side of a substrate. The first semiconductor layers interleave with the second semiconductor layers in a vertical direction. The first semiconductor layers and second semiconductor layers are etched into a plurality of stacks. The etching is performed such that a bottommost first semiconductor layer is etched to have a tapered profile in a cross-sectional view. The bottommost first semiconductor layer is replaced with a dielectric layer. The dielectric layer inherits the tapered profile of the bottommost first semiconductor layer. Gate structures are formed over the stacks. The gate structures each extend in a first horizontal direction. A first interconnect structure is formed over the gate structures. A second interconnect structure is formed over a back side of the substrate.
    Type: Application
    Filed: August 27, 2021
    Publication date: March 2, 2023
    Inventors: Shu-Wen Shen, Wei-Yang Lee, Yen-Po Lin, Jiun-Ming Kuo, Kuo-Yi Chao, Yuan-Ching Peng
  • Publication number: 20230068063
    Abstract: The present disclosure provides oligomeric compound comprising a modified oligonucleotide having a central region comprising one or more modifications. In certain embodiments, the present disclosure provides oligomeric compounds having an improved therapeutic index or an increased maximum tolerated dose.
    Type: Application
    Filed: March 17, 2022
    Publication date: March 2, 2023
    Applicant: Ionis Pharmaceuticals, Inc.
    Inventors: Punit P. Seth, Michael Oestergaard, Michael T. Migawa, Xue-hai Liang, Wen Shen, Stanley T. Crooke, Eric E. Swayze
  • Publication number: 20230043245
    Abstract: A method of manufacturing a semiconductor device includes forming M_1st segments in a first metallization layer including: forming first and second M_1st segments for which corresponding long axes extend in a first direction and are substantially collinear, the first and second M_1st segments being free from another instance of M_1st segment being between the first and second M_1st segments; and (A) where the first and second M_1st segments are designated for corresponding voltage values having a difference equal to or less than a reference value, separating the first and second M_1st segments by a first gap; or (B) where the first and second M_1st segments are designated for corresponding voltage values having a difference greater than the reference value, separating the first and second M_1st segments by a second gap, a second size of the second gap being greater than a first size of the first gap.
    Type: Application
    Filed: January 21, 2022
    Publication date: February 9, 2023
    Inventors: Ming-Cheng SYU, Po-Zeng KANG, Yung-Hsu CHUANG, Shu-Chin TAI, Wen-Shen CHOU, Yung-Chow PENG
  • Publication number: 20230037526
    Abstract: A semiconductor device includes a first semiconductor well. The semiconductor device includes a channel structure disposed above the first semiconductor well and extending along a first lateral direction. The semiconductor device includes a gate structure extending along a second lateral direction and straddling the channel structure. The semiconductor device includes a first epitaxial structure disposed on a first side of the channel structure. The semiconductor device includes a second epitaxial structure disposed on a second side of the channel structure, the first side and second side opposite to each other in the first lateral direction. The first epitaxial structure is electrically coupled to the first semiconductor well with a second semiconductor well in the first semiconductor well, and the second epitaxial structure is electrically isolated from the first semiconductor well with a dielectric layer.
    Type: Application
    Filed: January 28, 2022
    Publication date: February 9, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Chung Chen, Wen-Shen Chou, Yung-Chow Peng, Ya Yun Liu
  • Publication number: 20230023317
    Abstract: Systems and methods are provided for designing an integrated circuit device. In one example, a method for designing an integrated circuit device may include the operations of: receiving a schematic diagram of the integrated circuit device; generating, by a simulation program, a first transient simulation of the integrated circuit device based on the schematic diagram; determining from the first transient simulation of the integrated circuit device a plurality of maximum voltage change values between conductor networks (nets) within the schematic diagram of the integrated circuit device; storing the plurality of maximum voltage change values for the schematic diagram of the integrated circuit device in a computer readable medium; and utilizing, by a layout program, the stored plurality of maximum voltage change values to generate a layout design for the integrated circuit device according to one or more high voltage design constraints.
    Type: Application
    Filed: March 8, 2022
    Publication date: January 26, 2023
    Inventors: Shenggao Li, Szu-Chun Tsao, Wen-Shen Chou
  • Patent number: 11515393
    Abstract: A semiconductor device structure is provided. The device includes a plurality of semiconductor layers and a gate electrode layer surrounding each semiconductor layer of the plurality of semiconductor layers. The gate electrode layer comprises a first part and a second part below the first part. The second part comprises a first portion disposed adjacent a first semiconductor layer of the plurality of semiconductor layers, and an exterior surface of the first portion having a first radius of curvature, a second portion below the first portion and in contact with a second semiconductor layer of the plurality of semiconductor layers, and a third portion below the second portion and in contact with a third semiconductor layer of the plurality of semiconductor layers, and an exterior surface of the third portion having a second radius of curvature greater than the first radius of curvature.
    Type: Grant
    Filed: July 5, 2021
    Date of Patent: November 29, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Shu-Wen Shen
  • Publication number: 20220358273
    Abstract: Various techniques are disclosed for automatically generating sub-cells for a non-final layout of an analog integrated circuit. Device specifications and partition information for the analog integrated circuit is received. Based on the device specifications and the partition information, first cut locations for a first set of cuts to be made along a first direction of a non-final layout of the analog integrated circuit and second cut locations for a second set of cuts to be made along a second direction in the non-final layout are determined. The first set of cuts are made in the non-final layout at the cut locations to produce a temporary layout. The second set of cuts are made in the temporary layout at the cut locations to produce a plurality of sub-cells.
    Type: Application
    Filed: July 26, 2022
    Publication date: November 10, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Chiang Chang, Wen-Shen Chou, Yung-Chow Peng, Yung-Hsu Chuang, Yu-Tao Yang, Bindu Madhavi Kasina
  • Patent number: 11492617
    Abstract: In certain embodiments, the present disclosure provides methods comprising contacting a cell with a compound comprising a modified oligonucleotide complementary to a nucleic acid transcript. In certain such embodiments, the modified oligonucleotide does not interact or interacts poorly with a mRNP complex or granule. In certain such embodiments the modifications and/or motifs of the modified oligonucleotide do not promote interaction with a mRNP complex or granule. In certain embodiments, the present disclosure provides methods comprising contacting a cell with a compound comprising a modified oligonucleotide thereby reducing the size or amount of protein aggregation in the cell. In certain such embodiments, the protein aggregate is a mRNP granule. In certain such embodiments, the modifications and/or motifs of the modified oligonucleotide promote interaction with a protein aggregate, such as a mRNP granule, that results in disruption of the protein aggregate.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: November 8, 2022
    Assignee: Ionis Pharmaceuticals, Inc
    Inventors: C. Frank Bennett, Xue-hai Liang, Wen Shen
  • Patent number: D978572
    Type: Grant
    Filed: September 27, 2022
    Date of Patent: February 21, 2023
    Inventor: Wen Shen