Abstract: According to the present disclosure, an oral rehabilitation device includes an air bladder and a pumping member. The air bladder includes a cheek-side membrane and a teeth-side membrane, and the cheek-side membrane and the teeth-side membrane are arranged opposite to each other. The pumping member is communicated with the air bladder, and the pumping member is configured for inflating the air bladder. The cheek-side membrane and the teeth-side membrane extend toward the outside of the air bladder when the pumping member is inflating the air bladder, and an extension of the cheek-side membrane is larger than an extension of the teeth-side membrane.

Abstract: A semiconductor device structure is provided. The device includes a plurality of semiconductor layers and a gate electrode layer surrounding each semiconductor layer of the plurality of semiconductor layers. The gate electrode layer includes a first part, and a second part below the first part, the second part comprises a first portion, wherein an exterior surface of the first portion has a first radius of curvature, and a second portion below the first portion, and a third portion below the second portion, wherein an exterior surface of the third portion having a second radius of curvature different than the first radius of curvature.

Abstract: In a method of manufacturing a semiconductor device, a fin structure including a stacked layer of first and second semiconductor layers and a hard mask layer over the stacked layer is formed. A sacrificial cladding layer is formed over at least sidewalls of the exposed hard mask layer and stacked layer. An etching is performed to remove lateral portions of the sacrificial cladding layer, thereby leaving the sacrificial cladding layer on sidewalls of the exposed hard mask layer and stacked layer. A first dielectric layer and a second dielectric layer made of a different material than the first dielectric layer are formed. The second dielectric layer is recessed, and a third dielectric layer made of a different material than the second dielectric layer is formed on the recessed second dielectric layer. During the etching operation, a protection layer is formed over the sacrificial cladding layer.

Abstract: The present disclosure provides oligomeric compound comprising a modified oligonucleotide having a central region comprising one or more modifications. In certain embodiments, the present disclosure provides oligomeric compounds having an improved therapeutic index or an increased maximum tolerated dose.

Abstract: A plurality of first semiconductor layers and second semiconductor layers are formed over a front side of a substrate. The first semiconductor layers interleave with the second semiconductor layers in a vertical direction. The first semiconductor layers and second semiconductor layers are etched into a plurality of stacks. The etching is performed such that a bottommost first semiconductor layer is etched to have a tapered profile in a cross-sectional view. The bottommost first semiconductor layer is replaced with a dielectric layer. The dielectric layer inherits the tapered profile of the bottommost first semiconductor layer. Gate structures are formed over the stacks. The gate structures each extend in a first horizontal direction. A first interconnect structure is formed over the gate structures. A second interconnect structure is formed over a back side of the substrate.

Abstract: A semiconductor device includes a first semiconductor well. The semiconductor device includes a channel structure disposed above the first semiconductor well and extending along a first lateral direction. The semiconductor device includes a gate structure extending along a second lateral direction and straddling the channel structure. The semiconductor device includes a first epitaxial structure disposed on a first side of the channel structure. The semiconductor device includes a second epitaxial structure disposed on a second side of the channel structure, the first side and second side opposite to each other in the first lateral direction. The first epitaxial structure is electrically coupled to the first semiconductor well with a second semiconductor well in the first semiconductor well, and the second epitaxial structure is electrically isolated from the first semiconductor well with a dielectric layer.

Abstract: A method of manufacturing a semiconductor device includes forming M_1st segments in a first metallization layer including: forming first and second M_1st segments for which corresponding long axes extend in a first direction and are substantially collinear, the first and second M_1st segments being free from another instance of M_1st segment being between the first and second M_1st segments; and (A) where the first and second M_1st segments are designated for corresponding voltage values having a difference equal to or less than a reference value, separating the first and second M_1st segments by a first gap; or (B) where the first and second M_1st segments are designated for corresponding voltage values having a difference greater than the reference value, separating the first and second M_1st segments by a second gap, a second size of the second gap being greater than a first size of the first gap.

Abstract: Systems and methods are provided for designing an integrated circuit device. In one example, a method for designing an integrated circuit device may include the operations of: receiving a schematic diagram of the integrated circuit device; generating, by a simulation program, a first transient simulation of the integrated circuit device based on the schematic diagram; determining from the first transient simulation of the integrated circuit device a plurality of maximum voltage change values between conductor networks (nets) within the schematic diagram of the integrated circuit device; storing the plurality of maximum voltage change values for the schematic diagram of the integrated circuit device in a computer readable medium; and utilizing, by a layout program, the stored plurality of maximum voltage change values to generate a layout design for the integrated circuit device according to one or more high voltage design constraints.

Abstract: A semiconductor device structure is provided. The device includes a plurality of semiconductor layers and a gate electrode layer surrounding each semiconductor layer of the plurality of semiconductor layers. The gate electrode layer comprises a first part and a second part below the first part. The second part comprises a first portion disposed adjacent a first semiconductor layer of the plurality of semiconductor layers, and an exterior surface of the first portion having a first radius of curvature, a second portion below the first portion and in contact with a second semiconductor layer of the plurality of semiconductor layers, and a third portion below the second portion and in contact with a third semiconductor layer of the plurality of semiconductor layers, and an exterior surface of the third portion having a second radius of curvature greater than the first radius of curvature.

Abstract: Various techniques are disclosed for automatically generating sub-cells for a non-final layout of an analog integrated circuit. Device specifications and partition information for the analog integrated circuit is received. Based on the device specifications and the partition information, first cut locations for a first set of cuts to be made along a first direction of a non-final layout of the analog integrated circuit and second cut locations for a second set of cuts to be made along a second direction in the non-final layout are determined. The first set of cuts are made in the non-final layout at the cut locations to produce a temporary layout. The second set of cuts are made in the temporary layout at the cut locations to produce a plurality of sub-cells.

Abstract: In certain embodiments, the present disclosure provides methods comprising contacting a cell with a compound comprising a modified oligonucleotide complementary to a nucleic acid transcript. In certain such embodiments, the modified oligonucleotide does not interact or interacts poorly with a mRNP complex or granule. In certain such embodiments the modifications and/or motifs of the modified oligonucleotide do not promote interaction with a mRNP complex or granule. In certain embodiments, the present disclosure provides methods comprising contacting a cell with a compound comprising a modified oligonucleotide thereby reducing the size or amount of protein aggregation in the cell. In certain such embodiments, the protein aggregate is a mRNP granule. In certain such embodiments, the modifications and/or motifs of the modified oligonucleotide promote interaction with a protein aggregate, such as a mRNP granule, that results in disruption of the protein aggregate.

Abstract: A semiconductor device includes a hysteresis block configured to generate an output voltage at corresponding disabling enabling voltage levels and a core-voltage-gated (CVG) device configured to receive a core voltage, an input terminal of the hysteresis block is coupled to a control node. The CVG device is configured to alter a control voltage at the control node so as to cause the output voltage of the hysteresis block to be generated at the disabling voltage level in response to the core voltage being at or below a first trigger level. Additionally, the CVG device is configured to alter the control voltage at the control node so as to cause the output voltage of the hysteresis block to be generated at the enabling voltage level in response to the core voltage being at or above a second trigger level, the second trigger level being above the first trigger level.

Abstract: A semiconductor device structure is provided. The device includes a plurality of semiconductor layers and a gate electrode layer surrounding each semiconductor layer of the plurality of semiconductor layers. The gate electrode layer comprises a first part and a second part below the first part. The second part comprises a first portion disposed adjacent a first semiconductor layer of the plurality of semiconductor layers, and an exterior surface of the first portion having a first radius of curvature, a second portion below the first portion and in contact with a second semiconductor layer of the plurality of semiconductor layers, and a third portion below the second portion and in contact with a third semiconductor layer of the plurality of semiconductor layers, and an exterior surface of the third portion having a second radius of curvature greater than the first radius of curvature.

Abstract: In a method of manufacturing a semiconductor device, a fin structure including a stacked layer of first and second semiconductor layers and a hard mask layer over the stacked layer is formed. A sacrificial cladding layer is formed over at least sidewalls of the exposed hard mask layer and stacked layer. An etching is performed to remove lateral portions of the sacrificial cladding layer, thereby leaving the sacrificial cladding layer on sidewalls of the exposed hard mask layer and stacked layer. A first dielectric layer and a second dielectric layer made of a different material than the first dielectric layer are formed. The second dielectric layer is recessed, and a third dielectric layer made of a different material than the second dielectric layer is formed on the recessed second dielectric layer. During the etching operation, a protection layer is formed over the sacrificial cladding layer.

Abstract: Techniques for generating one or more non-final layouts for an analog integrated circuit are disclosed. The techniques include generating a non-final layout of an analog integrated circuit based on device specifications, partitioning the non-final layout into a plurality of sub-cells, merging the verified sub-cells to form a merged layout of the analog integrated circuit, and performing quality control checks on the merged layout. Additionally or alternatively, generating the non-final layout can include determining an allowable spacing between adjacent cells of different cell types or inserting one or more filler cells into a filler zone in the non-final layout.

Abstract: Various techniques are disclosed for automatically generating sub-cells for a non-final layout of an analog integrated circuit. Device specifications and partition information for the analog integrated circuit is received. Based on the device specifications and the partition information, first cut locations for a first set of cuts to be made along a first direction of a non-final layout of the analog integrated circuit and second cut locations for a second set of cuts to be made along a second direction in the non-final layout are determined. The first set of cuts are made in the non-final layout at the cut locations to produce a temporary layout. The second set of cuts are made in the temporary layout at the cut locations to produce a plurality of sub-cells.

Abstract: A reusable adhesive pad with embedded magnets consists of a layer of fibrous cloth with elasticity, a layer of silicone gel padding, and permanent magnets. The fibrous cloth with elasticity is made from fiber materials with a stretchable characteristic. The silicone gel padding is spread out fully and glued on one surface of the fibrous cloth with elasticity. In addition, the silicone gel padding is provided with holes that the permanent magnets with cylindrical or conical outers can be filled in and glued to the adhesive surface of the fibrous cloth with elasticity. Since the other sides of the permanent magnets protrude outwards the surface of the silicone gel padding, applying the invention to the human skin can perform the acupuncture and moxibustion treatment and the magneto-therapy to lessen painful discomfort.

Abstract: A method of generating a layout design of an integrated circuit includes forming an active zone and partitioning the active zone into a center portion between a first side portion and a second side portion. The method also includes forming a plurality of gate-strips and forming a routing line. The plurality of gate-strips includes a first group of gate-strips intersecting the active zone over first channel regions in the center portion, a second group of gate-strips intersecting the active zone over second channel regions in the center portion, a third group of gate-strips intersecting the active zone over third channel regions in the first side portion, and a fourth group of gate-strips intersecting the active zone over fourth channel regions in the second side portion.

Abstract: A semiconductor device and a method for manufacturing the semiconductor device are provided. The semiconductor device includes an insulating layer, a semiconductor layer, a plurality of isolation structures, a transistor, a first contact, a plurality of silicide layers, and a protective layer. The semiconductor layer is disposed on a front side of the insulating layer. The plurality of isolation structures are disposed in the semiconductor layer. The transistor is disposed on the semiconductor layer. The first contact is disposed beside the transistor and passes through one of the plurality of isolation structures and the insulating layer therebelow. The plurality of silicide layers are respectively disposed on a bottom surface of the first contact and disposed on a source, a drain, and a gate of the transistor. The protective layer is disposed between the first contact and the insulating layer.