Abstract: Techniques for generating one or more non-final layouts for an analog integrated circuit are disclosed. The techniques include generating a non-final layout of an analog integrated circuit based on device specifications, partitioning the non-final layout into a plurality of subcells, merging the verified sub-cells to form a merged layout of the analog integrated circuit, and performing quality control checks on the merged layout. Additionally or alternatively, generating the non-final layout can include determining an allowable spacing between adjacent cells of different cell types or inserting one or more filler cells into a filler zone in the non-final layout.

Abstract: Systems, methods, and devices are disclosed herein for developing a cell design. Operations of a plurality of electrical cells are simulated to collect a plurality of electrical parameters. A machine learning model is trained using the plurality of electrical parameters. The trained machine learning model receives data having cell layout design constraints. The trained machine learning model determines a cell layout for the received data based on the plurality of electrical parameters. The cell layout is provided for further characterization of electrical performance within the cell layout design constraints.

Abstract: A semiconductor device including a first active region having a first active configuration, a second active region having a second, and different, active configuration, and a transition cell arranged between the first and second active regions in which the transition cell has a transitional configuration that is different from and compatible with both the first active configuration and the second active configuration.

Abstract: A semiconductor device includes a first semiconductor well. The semiconductor device includes a channel structure disposed above the first semiconductor well and extending along a first lateral direction. The semiconductor device includes a gate structure extending along a second lateral direction and straddling the channel structure. The semiconductor device includes a first epitaxial structure disposed on a first side of the channel structure. The semiconductor device includes a second epitaxial structure disposed on a second side of the channel structure, the first side and second side opposite to each other in the first lateral direction. The first epitaxial structure is electrically coupled to the first semiconductor well with a second semiconductor well in the first semiconductor well, and the second epitaxial structure is electrically isolated from the first semiconductor well with a dielectric layer.

Abstract: Various techniques are disclosed for automatically generating sub-cells for a non-final layout of an analog integrated circuit. Device specifications and partition information for the analog integrated circuit is received. Based on the device specifications and the partition information, first cut locations for a first set of cuts to be made along a first direction of a non-final layout of the analog integrated circuit and second cut locations for a second set of cuts to be made along a second direction in the non-final layout are determined. The first set of cuts are made in the non-final layout at the cut locations to produce a temporary layout. The second set of cuts are made in the temporary layout at the cut locations to produce a plurality of sub-cells.

Abstract: A semiconductor device including a first active region having a first active configuration, a second active region having a second, and different, active configuration, and a transition cell arranged between the first and second active regions in which the transition cell has a transitional configuration that is different from and compatible with both the first active configuration and the second active configuration.

Abstract: The method in embodiments of this application includes: obtaining a plurality of types of data, where all of the plurality of types of data have different sources and different data types; performing knowledge extraction on the plurality of types of data to obtain a knowledge graph, where the knowledge graph includes a plurality of knowledge entities and an association relationship between the plurality of knowledge entities, and the plurality of knowledge entities include different data types; and performing knowledge representation on each knowledge entity by using a knowledge representation algorithm corresponding to a data type of each knowledge entity, and initializing a weight of the relationship between the plurality of knowledge entities in the knowledge graph, to obtain a vector graph, where the vector graph is used to train an artificial intelligence AI task model.

Abstract: A sensor for detecting a target analyte in a sample includes a pair of conducting electrodes that are separated by a gap. An insulator is disposed in the gap between the electrodes. Plural wells are defined by one of the electrodes and the insulator, to expose the other of the electrodes. The wells are configured to receive a sample including a target analyte. The target analyte, when present in the sample received in the wells, modulates an impedance between the electrodes. The modulated impedance, which is measurable with an applied electrical voltage, is indicative of the concentration of the target analyte in the sample. The wells can include antibodies immobilized inside the wells, to bind the target analyte, which can be a cytokine. Also provided are a method for label-free sensing of a target analyte in a sample, and a transcutaneous impedance sensor for label-free, in-situ biomarker detection.

Abstract: A semiconductor device includes a first semiconductor well. The semiconductor device includes a channel structure disposed above the first semiconductor well and extending along a first lateral direction. The semiconductor device includes a gate structure extending along a second lateral direction and straddling the channel structure. The semiconductor device includes a first epitaxial structure disposed on a first side of the channel structure. The semiconductor device includes a second epitaxial structure disposed on a second side of the channel structure, the first side and second side opposite to each other in the first lateral direction. The first epitaxial structure is electrically coupled to the first semiconductor well with a second semiconductor well in the first semiconductor well, and the second epitaxial structure is electrically isolated from the first semiconductor well with a dielectric layer.

Abstract: In a method of manufacturing a semiconductor device, a fin structure including a stacked layer of first and second semiconductor layers and a hard mask layer over the stacked layer is formed. A sacrificial cladding layer is formed over at least sidewalls of the exposed hard mask layer and stacked layer. An etching is performed to remove lateral portions of the sacrificial cladding layer, thereby leaving the sacrificial cladding layer on sidewalls of the exposed hard mask layer and stacked layer. A first dielectric layer and a second dielectric layer made of a different material than the first dielectric layer are formed. The second dielectric layer is recessed, and a third dielectric layer made of a different material than the second dielectric layer is formed on the recessed second dielectric layer. During the etching operation, a protection layer is formed over the sacrificial cladding layer.

Abstract: A plurality of first semiconductor layers and second semiconductor layers are formed over a front side of a substrate. The first semiconductor layers interleave with the second semiconductor layers in a vertical direction. The first semiconductor layers and second semiconductor layers are etched into a plurality of stacks. The etching is performed such that a bottommost first semiconductor layer is etched to have a tapered profile in a cross-sectional view. The bottommost first semiconductor layer is replaced with a dielectric layer. The dielectric layer inherits the tapered profile of the bottommost first semiconductor layer. Gate structures are formed over the stacks. The gate structures each extend in a first horizontal direction. A first interconnect structure is formed over the gate structures. A second interconnect structure is formed over a back side of the substrate.

Abstract: A bioprintable material is provided. The bioprintable material includes a hydrogel and microfilaments mixed in the hydrogel. The hydrogel includes a first collagen. The microfilament includes a second collagen. The diameter of the microfilament is ranging from 5 microns to 200 microns. The weight ratio of the microfilaments to the first collagen is ranging from 0.01:1 to 10:1.

Abstract: A semiconductor device structure is provided. The device includes a plurality of semiconductor layers vertically stacked, and a gate electrode layer comprising an upper portion disposed between two adjacent gate spacers, the upper portion having a first diameter. The gate electrode layer also includes a lower portion disposed below the upper portion including a first part surrounding each semiconductor layer of the plurality of semiconductor layers and a second part adjacent the first part, the second part comprising a first section having a second diameter that is less than the first diameter, a second section below the first section, the second section having a third diameter different than the second diameter, and a third section below the second section, wherein the third section has a fourth diameter different than the second diameter and the third diameter, wherein the first and second parts are formed as an integral.

Abstract: In certain embodiments, the present disclosure provides compounds and methods of increasing the amount or activity of a target protein in a cell. In certain embodiments, the compounds comprise a translation suppression element inhibitor. In certain embodiments, the translation suppression element inhibitor is a uORF inhibitor. In certain embodiments, the uORF inhibitor is an antisense compound.

Abstract: A semiconductor device includes an edge active cell, an inner active cell and a middle active cell. The edge active cell is located near an edge of the semiconductor device. The edge active cell includes a plurality of fingers. The inner active cell is adjacent to the edge active cell toward a central portion of the semiconductor device. The inner active cell includes a plurality of fingers and at least one of the plurality of fingers of the edge active cell is electrically connected to at least one of the plurality of fingers of the inner active cell. The middle active cell is located near the central portion of the semiconductor device. The middle active cell includes a plurality of fingers and each of the fingers of the middle active cell is electrically connected to each other.

Abstract: A swimming timer including a fluid container, a fluid channel, a fluid sensor, a control circuit board and a display device. The fluid channel is connected to the fluid container and the fluid sensor, and the control circuit board is wired with the fluid sensor and the display device. The fluid container is installed and mounted on a side-wall of a swimming lane. When a swimmer starts, turns and stops, the fluid container will be touched and compressed forcing the fluid inside to flow into the fluid channel. The fluid sensor detects the fluid flow and generates electronic signals accordingly for the control circuit board and the built-in timing and stopwatch program to use as the input commands of start, lap and stop to compute the swimming time and the number of swimming laps. The display device is to show the results for the swimmer reference.

Abstract: In a method of manufacturing a semiconductor device, a fin structure including a stacked layer of first and second semiconductor layers and a hard mask layer over the stacked layer is formed. A sacrificial cladding layer is formed over at least sidewalls of the exposed hard mask layer and stacked layer. An etching is performed to remove lateral portions of the sacrificial cladding layer, thereby leaving the sacrificial cladding layer on sidewalls of the exposed hard mask layer and stacked layer. A first dielectric layer and a second dielectric layer made of a different material than the first dielectric layer are formed. The second dielectric layer is recessed, and a third dielectric layer made of a different material than the second dielectric layer is formed on the recessed second dielectric layer. During the etching operation, a protection layer is formed over the sacrificial cladding layer.

Abstract: A semiconductor device includes a plurality of active area structures extending in parallel, first and second dummy gate layers spanning the plurality of active area structures, a first active device including first portions of the plurality of active area structures between the first and second dummy gate layers, a metal layer spanning the plurality of active area structures between the first and second dummy gate layers, and a pair of vias positioned at opposite ends of the metal layer. A first via of the pair of vias is configured to be electrically connected to ground, and a second via of the pair of vias is configured to be electrically connected to a current source and a circuit configured to measure a voltage at the node.