Abstract: The present invention proposes a packaging structure that integrates distance sensing device and temperature sensing device, and it is applied to small wearable devices such as earphones or watches. The combination of distance and temperature sensing allows the wearable device to accurately determine whether it is on the user's body, and then start temperature monitoring. It can collect ear temperature information more effectively and energy-saving.

Abstract: Disclosures of the present invention describe an optical proximity sensor, which is particularly designed to have functionality of canceling an ambient light noise and/or an optical crosstalk noise by using light-to-frequency conversion technique, and comprises: a controlling and processing circuit, a lighting unit, a light receiving unit, an analog adder, a first DAC unit, a second DAC unit, and a light-to-digital conversion (LDC) unit. In the controlling of the controlling and processing circuit, the first DAC unit and the second DAC unit would respectively generate a first compensation current signal and a second compensation current signal to the analog adder, such that a noise signal of ambient light and a noise signal of optical crosstalk existing in an optical current signal of object reflection light would be canceled by the two compensation current signals in the analog adder.

Abstract: The present invention provides a photosensor device with temperature compensation, which can adjust or calibrate the number, time and power of luminescence of light emitting elements under different ambient temperatures, so that the light signal values received by the photosensor device can be kept consistent or within the error range, there are multiple applications.

Abstract: The invention relates to a method, and an apparatus for accessing to data in response to a power-supply event. The method, performed by a flash controller, includes steps for: reading a plurality of physical pages of data in a current block from a flash module during a sudden power off recovery procedure; determining whether a power-supply event has occurred according to an error correction result corresponding to read physical pages; reconstructing a first flash-to-host mapping (F2H) table to include physical-to-logical mapping (P2L) information from the 0th page to a page before a last valid page in the current block when the power-supply event has occurred; and programming the reconstructed first F2H table into a location of the flash module.

Abstract: The invention introduces a non-transitory computer program product for handling a sudden power off recovery (SPOR) to include program code to: drive a flash access interface to read pages of a current block in sequence after a power restart subsequent to a sudden power off (SPO); mark the last correct page of the current block according to page read statuses for the current block; configure n1 pages after the next page of the last correct page of the current block as dummy pages; and drive the flash access interface to store data of the last correct page and its previous n2-1 pages of the current block in empty pages after the last dummy page of the current block, wherein any of n1 and n2 is a positive integer.

Abstract: The invention relates to a method, and an apparatus for accessing to data in response to a power-supply event. The method, performed by a flash controller, includes steps for: repeatedly detecting whether a voltage supplied to the flash controller is lower than a first threshold; and issuing a program command to a flash module for programming data into the flash module and performing a supervision procedure when the voltage is lower than the first threshold. The supervision procedure includes steps for: repeatedly detecting whether the voltage is lower than a second threshold during a time period when issuing the program command to the flash module until transmitting the data to the flash module completely; and cancelling the program command when the voltage is lower than the second threshold.

Abstract: A low power operation method provides an apparatus with a data transmission rate. A power management unit (PMU), which is not influenced by voltage, process, and temperature, biases a high frequency oscillator (HOSC) and makes the HOSC generate a steady and high precision clock. The clock of the HOSC is used to modify a timing length of a timer which is referenced by a low frequency oscillator (LOSC) without PMU. At last, through the modified timing length, the apparatus achieves high precision periods and data transmissions with compensation for voltage, process, and temperature. Thus, the data transmission cycles of the apparatus maintain stable and robust even if the apparatus applies duty cycle usage of the HOSC and the PMU for reducing power consumption with actions of turning on and turning off. Consequently, the periodic apparatus maintains data transmission rate with the low power consumption advantage of non-periodic apparatus.

Abstract: A low power operation method provides an apparatus with a data transmission rate. A power management unit (PMU), which is not influenced by voltage, process, and temperature, biases a high frequency oscillator (HOSC) and makes the HOSC generate a steady and high precision clock. The clock of the HOSC is used to modify a timing length of a timer which is referenced by a low frequency oscillator (LOSC) without PMU. At last, through the modified timing length, the apparatus achieves high precision periods and data transmissions with compensation for voltage, process, and temperature. Thus, the data transmission cycles of the apparatus maintain stable and robust even if the apparatus applies duty cycle usage of the HOSC and the PMU for reducing power consumption with actions of turning on and turning off. Consequently, the periodic apparatus maintains data transmission rate with the low power consumption advantage of non-periodic apparatus.

Abstract: A flash memory controller includes a read-only memory, a microprocessor and a buffer memory, wherein the buffer memory includes a data temporary storage area having continuous addresses. When the flash memory controller receives data from a host device, the microprocessor determines whether there is enough space between the last stored data in the data temporary storage area and an end address of the data temporary storage area to store the entire content of the data. If there is not enough space between the last stored data in the data temporary storage area and the end address to store the entire content of the data, the microprocessor directly stores the data from a starting address in the data temporary storage area, without writing any part of the data to the area before the end address of the data temporary storage area.

Abstract: A flash memory controller includes a read-only memory, a microprocessor and a buffer memory, wherein the buffer memory includes a data temporary storage area having continuous addresses. When the flash memory controller receives data from a host device, the microprocessor determines whether there is enough space between the last stored data in the data temporary storage area and an end address of the data temporary storage area to store the entire content of the data. If there is not enough space between the last stored data in the data temporary storage area and the end address to store the entire content of the data, the microprocessor directly stores the data from a starting address in the data temporary storage area, without writing any part of the data to the area before the end address of the data temporary storage area.

Abstract: A flash memory controller is configured to access a flash memory module, and the flash memory controller includes a read-only memory and a microprocessor. When the flash memory controller is powered on and performs an initialization operation, within a predetermined time range of the initialization operation, the microprocessor determines whether a number of spare blocks in the flash memory module is lower than a first threshold value to determine whether to perform a garbage collection operation. When an elapsed time since the flash memory controller is powered on exceeds the predetermined time range, the microprocessor determines whether a number of spare blocks in the flash memory module is lower than a second threshold to determine whether to perform another garbage collection operation, where the second threshold value is lower than the first threshold.

Abstract: A digital device is provided. The digital device uses three states, including a ground (GND) state, a voltage (VDD) state, and a FLOAT state. On designing a chip, two storage units and a pad circuit are set inside; the pad circuit comprises a current limiter and two switches; and less ports contained are required than the conventional. That is, one port obtains three states. As comparing to the conventional having only two states, the present invention uses the port connected with two storage units in the pad circuit for obtaining the three states; a circuit featuring “pull up” and “pull down” is used to identify the state of connection of the port; and the port determines a plurality of definitions through the three states of GND, VDD and FLOAT. Thus, a pad is saved for reducing the space and cost of the chip.

Abstract: A data storage device includes a memory device and a memory controller. The memory controller is configured to configure a first predetermined memory block which is an SLC memory block and a second predetermined memory block which is a MLC memory block as buffers to receive data. The memory controller determines to use which scheme to receive data in a predetermined period dynamically according to an amount of valid data stored in the memory device. When the memory controller determines to use a first scheme, the memory controller uses the first predetermined memory block to receive data. When the memory controller determines to use a second scheme, the memory controller uses the first predetermined memory block and the second predetermined memory block to receive data. When the memory controller determines to use a third scheme, the memory controller uses the second predetermined memory block to receive data.

Abstract: The invention relates to a method, and an apparatus for accessing to data in response to a power-supply event The method, performed by a flash controller, includes steps for: repeatedly detecting whether a voltage supplied to the Hash controller is lower than a first threshold; and issuing a program command to a flash module for programming data into the flash module and performing a supervision procedure when the voltage is lower than the first threshold. The supervision procedure includes steps for: repeatedly detecting whether the voltage is lower than a second threshold during a time period when issuing the program command to the flash module until transmitting the data to the flash module completely; and cancelling the program command when the voltage is lower than the second threshold.

Abstract: The present invention provides a flash memory controller, wherein the flash memory controller includes a read-only memory, a microprocessor and a decoder, wherein the read-only memory is configured to store a program code, and the microprocessor is configured to execute the program code to access a flash memory module. In the operations of the flash memory controller, when the flash memory controller is powered on, the microcontroller reads a plurality of pages of a specific block of the flash memory module, and the decoder decodes data of the plurality of pages. When any one of the pages cannot be decoded successfully, the microcontroller seals the specific block, and increase a priority of the specific block for quality detection or garbage collection.

Abstract: A flash memory controller is disclosed. The flash memory controller is configured to access a flash memory module, wherein the flash memory module includes a plurality of first blocks and a plurality of second blocks, and the flash memory controller includes a microprocessor and a read-only memory storing a program code. When the flash memory controller is powered on, when the flash memory controller is required to write data into the flash memory module, the microprocessor writes the data into the plurality of first blocks only; and the microprocessor writes subsequent data into the second blocks only when a quantity of the plurality of first blocks written by the flash memory controller after power on is greater than a threshold value.

Abstract: A smart method is provided for a low-current oscillatory circuitry. The circuitry comprises an oscillator and a microcontroller unit (MCU). The oscillator comprises a proportional-to-absolute-temperature circuit connecting to a low-voltage regulator. The low-voltage regulator connects to a PMOS diode array and a delay unit circuit. The PMOS diode array connects to the MCU. The delay unit circuit connects to the MCU and a voltage converter. The method includes a normal temperature compensation algorithm; a smart learning algorithm of extra-high temperature compensation; and an ultra-high temperature compensation algorithm. Thus, clock variations are compensated; output frequency is stable and not affected by voltage or temperature variations; and process variations are suppressed. When process variations appear, there are not be too many errors generated.

Abstract: A light sensor device is provided. It is controlled with a dual-mode master-and-slave microcontroller unit (MCU) application. An MCU is embedded into a light sensor chip. The original dual-mode master-and-slave dual-CPU architectures are combined to be operated as a single-CPU architecture. Since the original circuit pin design is followed, it is possible to be compatible with the old circuit design. The present invention uses a single-CPU architecture to directly control light sensors. Through the configuration of RAM, an inter-integrated circuit bus (I2C I/F) can be redirected to an internal non-volatile memory to switch the operational mode of the light sensor chip from a slave machine to a host machine which switches off the interrupt pin and, then, turns to a GPIO pin. Thus, the present invention provides a simple single-CPU architecture with easy use and effectively-lowered cost.

Abstract: The invention introduces a non-transitory computer program product for handling a sudden power off recovery (SPOR) to include program code to: drive a flash access interface to read pages of a current block in sequence after a power restart subsequent to a sudden power off (SPO); mark the last correct page of the current block according to page read statuses for the current block; configure n1 pages after the next page of the last correct page of the current block as dummy pages; and drive the flash access interface to store data of the last correct page and its previous n2-1 pages of the current block in empty pages after the last dummy page of the current block, wherein any of n1 and n2 is a positive integer.

Abstract: The invention introduces a non-transitory computer program product for handling a sudden power off recovery (SPOR) to include program code to: drive a flash access interface to read pages of a current block in sequence after a power restart subsequent to a sudden power off (SPO); mark the last correct page of the current block according to page read statuses for the current block; drive the flash access interface to read protection information of pages of a temporary block in sequence, so as to mark the first incorrect page of the temporary block; and drop data of the first incorrect page and pages thereafter of the temporary block.