Abstract: The present invention provides a flash memory controller, wherein the flash memory controller includes a read-only memory, a microprocessor and a decoder, wherein the read-only memory is configured to store a program code, the microprocessor is configured to execute the program code to access a flash memory module, and the decoder includes a hard decoding function and a soft decoding function. In the operations of the flash memory controller, when the flash memory controller and the flash memory module are powered-on, the flash memory controller reads data from a specific block of the flash memory module, and the decoder determines if disabling the soft decoding function or not according to a status of the specific block or a status of the data.

Abstract: A data storage device includes a memory controller and a memory device. The memory device includes a current memory block. The memory controller is coupled to the memory device and configured to access the memory device. In response to detection of a sudden power-off that has occurred before the memory device is powered up, the memory controller is configured to find a last valid page and a last valid word line corresponding to the last valid page by scanning a plurality of pages in the current memory block, and determine whether to use one or more empty pages belonging to a word line group that is the same as that of the last valid page according to a read count and an erase count of the current memory block.

Abstract: A light sensor device is provided. It is controlled with a dual-mode master-and-slave microcontroller unit (MCU) application. An MCU is embedded into a light sensor chip. The original dual-mode master-and-slave dual-CPU architectures are combined to be operated as a single-CPU architecture. Since the original circuit pin design is followed, it is possible to be compatible with the old circuit design. The present invention uses a single-CPU architecture to directly control light sensors. Through the configuration of RAM, an inter-integrated circuit bus (I2C I/F) can be redirected to an internal non-volatile memory to switch the operational mode of the light sensor chip from a slave machine to a host machine which switches off the interrupt pin and, then, turns to a GPIO pin. Thus, the present invention provides a simple single-CPU architecture with easy use and effectively-lowered cost.

Abstract: A power recovery technique for a data storage device having a non-volatile memory and a control unit is shown. The non-volatile memory is programmed using one-shot programming, wherein N pages are programmed in one round of one-shot programming and N is a number greater than one. A control unit corrects the final page indicator of an active block of the non-volatile memory in a power recovery procedure to cope with a sudden power-off event, to point the final page indicator to a final page among N pages of one round of one-shot programming.

Abstract: A data storage device includes a memory device and a memory controller. The memory controller is configured to configure a first predetermined memory block which is an SLC memory block and a second predetermined memory block which is a MLC memory block as buffers to receive data. The memory controller determines to use which scheme to receive data in a predetermined period dynamically according to an amount of valid data stored in the memory device. When the memory controller determines to use a first scheme, the memory controller uses the first predetermined memory block to receive data. When the memory controller determines to use a second scheme, the memory controller uses the first predetermined memory block and the second predetermined memory block to receive data. When the memory controller determines to use a third scheme, the memory controller uses the second predetermined memory block to receive data.

Abstract: A power recovery technique for a data storage device having a non-volatile memory and a control unit is provided. When the data storage device regains power, the control unit writes dummy data to the nonvolatile memory, starting from the next page of a final page indicated by a final page indicator until the first word line group is finished. The first word line group contains an empty page indicated by an empty page indicator. In this manner, user data is protected from being written to an unreliable area.

Abstract: A data storage device includes a memory device and a controller. The memory device includes multiple memory blocks. The memory blocks include single-level cell blocks and multiple-level cell blocks. The controller is coupled to the memory device. When the controller executes a predetermined procedure to write data stored in the single-level cell blocks into the multiple-level cell blocks, the controller is configured to determine whether a valid page count corresponding to each single-level cell block is greater than a threshold, and when the valid page count corresponding to more than one single-level cell block is greater than the threshold, the controller is configured to execute a first merge procedure to directly write the data stored in the single-level cell blocks with the valid page count greater than the threshold into one or more of the multiple-level cell blocks.

Abstract: A flash memory controller is disclosed. The flash memory controller is configured to access a flash memory module, wherein the flash memory module includes a plurality of first blocks and a plurality of second blocks, and the flash memory controller includes a microprocessor and a read-only memory storing a program code. When the flash memory controller is powered on, when the flash memory controller is required to write data into the flash memory module, the microprocessor writes the data into the plurality of first blocks only; and the microprocessor writes subsequent data into the second blocks only when a quantity of the plurality of first blocks written by the flash memory controller after power on is greater than a threshold value.

Abstract: Disclosures of the present invention particularly describe oscillator circuit with temperature compensation function, consisting of a fully differential amplifier, a current mirror unit, a bias current supplying unit, a compensation unit, and a reference signal generating unit. A variety of experimental data have proved that, based on the normal operation of the compensation unit and the reference signal generating unit, an oscillation frequency of this oscillator circuit would be maintained at same level even if the ambient temperature continuously increases. Therefore, because the frequency drift due to temperature variation would not occur in the oscillator circuit of the present invention, the novel oscillator circuit is potential oscillator to replace the conventional oscillators applied in analog-to-digital convertors or time-to-digital convertors.

Abstract: The present invention provides a flash memory controller, wherein the flash memory controller includes a read-only memory, a microprocessor and a decoder, wherein the read-only memory is configured to store a program code, and the microprocessor is configured to execute the program code to access a flash memory module. In the operations of the flash memory controller, when the flash memory controller is powered on, the microcontroller reads a plurality of pages of a specific block of the flash memory module, and the decoder decodes data of the plurality of pages. When any one of the pages cannot be decoded successfully, the microcontroller seals the specific block, and increase a priority of the specific block for quality detection or garbage collection.

Abstract: A load lock system for charged particle beam imaging with a particle shielding plate, a bottom seal plate and a plurality of sensor units is provided. The sensor units are located above the wafer, the shield plate is designed to have a few number of screws, and the bottom seal plate contains no cable, no contact sensors and fewer screws used. In the invention, the system is designed to improve the contamination particles from components in the load lock system of charged particle beam inspection tool and also to simplify its assembly.

Abstract: A data storage device includes a memory device and a controller. The memory device includes multiple memory blocks. Each memory block includes multiple pages. The controller is coupled to the memory device and includes an ECC engine configured to check and correct errors that have occurred in data stored in the memory blocks. When a number of error bits in a page of one of the memory blocks exceeds a threshold, the controller is configured to add a block number of the memory block in a predetermined queue and when a garbage collection procedure has been triggered, the controller is configured to perform garbage collection on the memory block.

Abstract: A data storage device includes a memory device and a controller. The memory device includes a first buffer, a second buffer, and a backup memory block. The first buffer is an MLC block and the second buffer is an SLC block. The controller is coupled to the memory device, receives a write command to write predetermined data in the memory device and determines whether the predetermined data has to be written into different buffers. When the controller determines that the predetermined data has to be written into different buffers, the controller writes a portion of the predetermined data that has been written in one or more predetermined pages of the first buffer into the backup memory block.

Abstract: A data storage device includes a memory device and a controller. The memory device includes multiple memory blocks. The memory blocks include single-level cell blocks and multiple-level cell blocks. The controller is coupled to the memory device. When the controller executes a predetermined procedure to write data stored in the single-level cell blocks into the multiple-level cell blocks, the controller is configured to determine whether a valid page count corresponding to each single-level cell block is greater than a threshold, and when the valid page count corresponding to more than one single-level cell block is greater than the threshold, the controller is configured to execute a first merge procedure to directly write the data stored in the single-level cell blocks with the valid page count greater than the threshold into one or more of the multiple-level cell blocks.

Abstract: A data storage device includes a memory controller and a memory device. The memory device includes a current memory block. The memory controller is coupled to the memory device and configured to access the memory device. In response to detection of a sudden power-off that has occurred before the memory device is powered up, the memory controller is configured to find a last valid page and a last valid word line corresponding to the last valid page by scanning a plurality of pages in the current memory block, and determine whether to use one or more empty pages belonging to a word line group that is the same as that of the last valid page according to a read count and an erase count of the current memory block.

Abstract: The present invention provides a flash memory controller, wherein the flash memory controller includes a read-only memory, a microprocessor and a decoder, wherein the read-only memory is configured to store a program code, the microprocessor is configured to execute the program code to access a flash memory module, and the decoder includes a hard decoding function and a soft decoding function. In the operations of the flash memory controller, when the flash memory controller and the flash memory module are powered-on, the flash memory controller reads data from a specific block of the flash memory module, and the decoder determines if disabling the soft decoding function or not according to a status of the specific block or a status of the data.

Abstract: A data storage device includes a memory device, an SRAM and a controller. The memory device includes a first buffer configured to store data of a plurality of consecutive logical pages. The SRAM stores a first mapping table. The first mapping table records which logical page the data stored in each physical page of the first buffer directs to. The controller is coupled to the memory device and the SRAM. When the controller performs an erase operation to erase the data stored in the first buffer in response to an erase command, the controller checks whether an interrupt signal or a reset command issued by a host device has been received every time the erase operations of a predetermined number (M) of logical pages have finished. The predetermined number (M) is a positive integer greater than 1.

Abstract: A flash memory control technology with high reliability. In a power recovery process, a microcontroller is configured to duplicate a last write page of a run-time write block of a flash memory and thereby generate a duplicated page in the run-time write block to replace the last write page for reliability enhancement.

Abstract: A method for reusing a destination block related to garbage collection (GC) in a memory device, the associated memory device and the controller thereof, and the associated electronic device are provided. The method may include: when writing any page of a subset of a plurality of pages of the destination block in a GC procedure, writing valid data and source information into a data region and a spare region of the page, respectively, wherein a power-off event occurs during writing the destination block; after the power-off event ends, performing empty-page search in the destination block to find the last valid page within the destination block; and writing a set of subsequent valid data obtained from the source block into a subsequent page within the destination block, to reuse the destination block.

Abstract: A method for reusing a destination block related to garbage collection (GC) in a memory device, the associated memory device and the controller thereof, and the associated electronic device are provided. The method may include: when writing any page of a subset of a plurality of pages of the destination block in a GC procedure, writing valid data and source information into a data region and a spare region of the page, respectively, wherein a power-off event occurs during writing the destination block; after the power-off event ends, performing empty-page search in the destination block to find the last valid page within the destination block; and writing a set of subsequent valid data obtained from the source block into a subsequent page within the destination block, to reuse the destination block.