Abstract: A method of manufacturing a semiconductor device includes: coupling a semiconductor die to a protection layer; forming a first redistribution layer over the semiconductor die, wherein the first redistribution layer includes a first conductive plate of an antenna structure and a first dielectric layer laterally surrounding the first conductive plate; etching the first dielectric layer to form a recess exposing the first conductive plate; filling the recess with a second dielectric material to form an insulating film; and forming a second redistribution layer including a second conductive plate of the antenna structure over the insulating film. The insulating film electrically isolates the first conductive plate from the second conductive plate, wherein one of the first conductive plate and the second conductive plate is configured to radiate or receive electromagnetic wave. The insulating film has a thickness associated with a main resonance frequency of the antenna structure.

Abstract: A package includes a first redistribution structure, a die, an encapsulant, a second redistribution structure, and an inductor. The die is disposed on the first redistribution structure. The encapsulant laterally encapsulates the die. The second redistribution structure is over the die and the encapsulant. The inductor includes a first portion, a second portion, and a third portion. The first portion is embedded in the first redistribution structure. The second portion is embedded in the encapsulant and is connected to the first and third portions of the inductor. The third portion is embedded in the second redistribution structure.

Abstract: A device includes a ground plane electrically connected to a proximal end of at least one conductive pillar and an antenna pad substantially parallel to the ground plane, wherein the antenna pad is separated from a distal end of the at least one conductive pillar by a dielectric pad having a first dielectric constant, wherein the ground plane, the at least one conductive pillar, and the dielectric pad surround an antenna cavity filled with a dielectric fill material having a second dielectric constant different from the first dielectric constant.

Abstract: A semiconductor structure includes a first dielectric waveguide, a second dielectric waveguide, a first inter-level dielectric (ILD) material, a first transmitter coupling structure and a second transmitter coupling structure. The first and second dielectric waveguides are disposed one over the other. The first dielectric waveguide is configured to guide a first electromagnetic signal. The second dielectric waveguide is configured to guide a second electromagnetic signal. The first and second electromagnetic signals have different frequencies. The first ILD material is disposed between the first and second dielectric waveguides. The first transmitter coupling structure is configured to couple a first driver signal generated by a transmitter die to the first dielectric waveguide, and accordingly produce the first electromagnetic signal.

Abstract: A semiconductor device is disclosed. The semiconductor device includes a first die on a first substrate, a second die on a second substrate separate from the first substrate, a transmission line in a redistribution layer on a wafer, and a magnetic structure surrounds the transmission line. The first transmission line electrically connects the first die and the second die. The magnetic structure is configured to increase the characteristic impedance of the transmission line, which can save the current and power consumption of a current mirror and amplifier in a 3D IC chip-on-wafer-on-substrate (CoWoS) semiconductor package.

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a polymer base layer; a backside redistribution layer (RDL) over the polymer base layer; a molding layer over the backside RDL; a polymer layer over the molding layer; a front side RDL over the polymer layer; and a metal-insulator-metal (MIM) capacitor vertically passing through the molding layer, the MIM capacitor including a first electrode, an insulation layer and a second electrode, wherein the insulation layer surrounds the first electrode, and the second electrode surrounds the insulation layer, and the molding layer surrounds the second electrode. An associated method for manufacturing a semiconductor structure is also disclosed.

Abstract: A method of manufacturing a semiconductor package includes: coupling a semiconductor die to a protection layer; forming a first redistribution layer over the semiconductor die, wherein the first redistribution layer includes a first conductive plate and a first dielectric material laterally surrounding the first conductive plate; forming a recess in the first redistribution layer, wherein the recess is over the first conductive plate and defined by the first dielectric material; depositing an insulating film in the recess with a second dielectric material of a dielectric constant greater than a dielectric constant of the first dielectric material; and forming a second redistribution layer including a second conductive plate over the insulating film. The insulating film electrically isolates the first conductive plate from the second conductive plate, and one of the first conductive plate and the second conductive plate is configured to radiate or receive electromagnetic wave.

Abstract: A semiconductor device is disclosed. The semiconductor device includes a first die on a first substrate, a second die on a second substrate separate from the first substrate, a transmission line in a redistribution layer on a wafer, and a magnetic structure surrounds the transmission line. The first transmission line electrically connects the first die and the second die. The magnetic structure is configured to increase the characteristic impedance of the transmission line, which can save the current and power consumption of a current mirror and amplifier in a 3D IC chip-on-wafer-on-substrate (CoWoS) semiconductor package.

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a polymer base layer; a backside redistribution layer (RDL) over the polymer base layer; a molding layer over the backside RDL; a polymer layer over the molding layer; a front side RDL over the polymer layer; and a metal-insulator-metal (MIM) capacitor vertically passing through the molding layer, the MIM capacitor including a first electrode, an insulation layer and a second electrode, wherein the insulation layer surrounds the first electrode, and the second electrode surrounds the insulation layer, and the molding layer surrounds the second electrode. An associated method for manufacturing a semiconductor structure is also disclosed.

Abstract: The present disclosure describes a method of forming a metal insulator metal (MIM) decoupling capacitor that can be integrated (or embedded) into a 3D integrated circuit package such as, for example, a chip-on-wafer-on-substrate (CoWoS) chip package or an integrated fan-out (InFO) chip package. For example, the method includes providing a glass carrier with a protective layer over the glass carrier. The method also includes forming a capacitor on the protective layer by: forming a bottom metal layer on a portion of the protective layer; forming one or more first metal contacts and a second metal contact on the bottom metal layer, where the one or more first metal contacts have a width larger than the second metal contact; forming a dielectric layer on the one or more first metal contacts; and forming a top metal layer on the dielectric layer.

Abstract: A semiconductor arrangement is provided. The semiconductor arrangement includes a molding layer and a first capacitor. The first capacitor includes a first vertical conductive structure within the molding layer, a second vertical conductive structure within the molding layer, and a first high-k dielectric material between the first vertical conductive structure and the second vertical conductive structure.

Abstract: A device includes an interposer, a plurality of conductive through vias (TVs), a conductive element, and a redistribution line (RDL). The conductive TVs extend from a bottom surface of the interposer to a top surface of the interposer. The conductive element is over the bottom surface of the interposer. The RDL is over the top surface of the interposer. The RDL, the conductive TVs, and the conductive element are connected to form an inductor.

Abstract: A method of manufacturing a semiconductor package includes: coupling a semiconductor die to a protection layer; forming a first redistribution layer over the semiconductor die, wherein the first redistribution layer includes a first conductive plate and a first dielectric material laterally surrounding the first conductive plate; forming a recess in the first redistribution layer, wherein the recess is over the first conductive plate and defined by the first dielectric material; depositing an insulating film in the recess with a second dielectric material of a dielectric constant greater than a dielectric constant of the first dielectric material; and forming a second redistribution layer including a second conductive plate over the insulating film. The insulating film electrically isolates the first conductive plate from the second conductive plate, and one of the first conductive plate and the second conductive plate is configured to radiate or receive electromagnetic wave.

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a polymer base layer; a backside redistribution layer (RDL) over the polymer base layer; a molding layer over the backside RDL; a polymer layer over the molding layer; a front side RDL over the polymer layer; and a metal-insulator-metal (MIM) capacitor vertically passing through the molding layer, the MIM capacitor including a first electrode, an insulation layer and a second electrode, wherein the insulation layer surrounds the first electrode, and the second electrode surrounds the insulation layer, and the molding layer surrounds the second electrode. An associated method for manufacturing a semiconductor structure is also disclosed.

Abstract: A semiconductor structure includes a first dielectric waveguide, a second dielectric waveguide, a first inter-level dielectric (ILD) material, a first transmitter coupling structure and a second transmitter coupling structure. The first and second dielectric waveguides are disposed one over the other. The first dielectric waveguide is configured to guide a first electromagnetic signal. The second dielectric waveguide is configured to guide a second electromagnetic signal. The first and second electromagnetic signals have different frequencies. The first ILD material is disposed between the first and second dielectric waveguides. The first transmitter coupling structure is configured to couple a first driver signal generated by a transmitter die to the first dielectric waveguide, and accordingly produce the first electromagnetic signal.

Abstract: A semiconductor structure is disclosed that includes a dielectric waveguide, a first transmission electrode and a second transmission electrode, and a first receiver electrode and a second receiver electrode. The first transmission electrode and the second transmission electrode that are disposed over and below the dielectric waveguide, respectively, and the first transmission electrode and the second transmission electrode are symmetric with respect to the dielectric waveguide. The first receiver electrode and a second receiver electrode that are disposed over and below the dielectric waveguide, respectively, and the first receiver electrode and the second receiver electrode are symmetric with respect to the dielectric waveguide. The dielectric waveguide is configured to receive a transmission signal from a driver circuit through the first transmission electrode and to transmit the received transmission signal to a receiver circuit through the first receiver electrode.

Abstract: A three-Dimensional Integrated Circuit (3DIC) Chip on Wafer on Substrate (CoWoS) packaging structure or system includes a silicon oxide interposer with no metal ingredients, and with electrically conductive TVs and RDLs. The silicon oxide interposer has a first surface and a second surface opposite to the first surface. The electrically conductive TVs penetrate through the silicon oxide interposer. The electrically interconnected RDLs are disposed over the first surface of the silicon oxide interposer, and are electrically coupled or connected to a number of the conductive TVs.

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a polymer base layer; a backside redistribution layer (RDL) over the polymer base layer; a molding layer over the backside RDL; a polymer layer over the molding layer; a front side RDL over the polymer layer; and a metal-insulator-metal (MIM) capacitor vertically passing through the molding layer, the MIM capacitor including a first electrode, an insulation layer and a second electrode, wherein the insulation layer surrounds the first electrode, and the second electrode surrounds the insulation layer, and the molding layer surrounds the second electrode. An associated method for manufacturing a semiconductor structure is also disclosed.

Abstract: A semiconductor device includes a semiconductor substrate and an interconnect structure over the semiconductor substrate. The interconnect structure includes a magnetic core and a conductive coil winding around the magnetic core and electrically insulated from the magnetic core. The conductive coil includes horizontally-extending conductive lines and vertically-extending conductive vias electrically connecting the conductive lines.

Abstract: The present disclosure provides a semiconductor package device, which includes a semiconductor die and a redistribution layer disposed over and electrically coupled to the semiconductor die. The redistribution layer includes a first conductive plate, a second conductive plate disposed over the first conductive plate, an insulating film between the first conductive plate and the second conductive plate, and a first dielectric material encapsulating the first conductive plate, the second conductive plate and the insulating film. The first conductive plate and the second conductive plate are configured as an antenna plane and a ground plane, respectively.