Abstract: A semiconductor arrangement in fan out packaging has a molding compound adjacent a side of a semiconductor die. A magnetic structure is disposed above the molding compound, above the semiconductor die, and around a transmission line coupled to an integrated circuit of the semiconductor die. The magnetic structure has a top magnetic portion, a bottom magnetic portion, a first side magnetic portion, and a second side magnetic portion. The first side magnetic portion and the second side magnetic portion are coupled to the top magnetic portion and to the bottom magnetic portion. The first side magnetic portion and the second side magnetic portion have tapered sidewalls.

Abstract: An antenna structure includes a ground plane in a first metal layer of an integrated circuit (IC) package, a patch in a second metal layer of the IC package, a cavity structure between the ground plane and the patch, and a high-k dielectric layer between the ground plane and the patch.

Abstract: A semiconductor structure includes a substrate; an interconnect structure formed over the substrate and including a dielectric layer over the substrate, a first conductive member formed within the dielectric layer and a second conductive member formed within the dielectric layer; a waveguide formed between the first conductive member and the second conductive member; a first die disposed over the interconnect structure and electrically connected to the first conductive member; and a second die disposed over the interconnect structure and electrically connected to the second conductive member, wherein the waveguide is coupled with the first conductive member and the second conductive member.

Abstract: The present disclosure describes a method of forming a metal insulator metal (MIM) decoupling capacitor that can be integrated (or embedded) into a 3D integrated circuit package such as, for example, a chip-on-wafer-on-substrate (CoWoS) chip package or an integrated fan-out (InFO) chip package. For example, the method includes providing a glass carrier with a protective layer over the glass carrier. The method also includes forming a capacitor on the protective layer by: forming a bottom metal layer on a portion of the protective layer; forming one or more first metal contacts and a second metal contact on the bottom metal layer, where the one or more first metal contacts have a width larger than the second metal contact; forming a dielectric layer on the one or more first metal contacts; and forming a top metal layer on the dielectric layer.

Abstract: A device includes an insulating layer disposed over a silicon substrate. The insulating layer includes a core insulating area and a peripheral insulating area. A trench laterally encloses the core insulating area and separates the core insulating area from the peripheral insulating area. A magnetic winding coil is disposed within the trench and separates the core insulating area from the peripheral insulating area. A conductive inner core is disposed within the core insulating area and is surrounded by the magnetic winding coil. The conductive inner core is made of a first material that is electrically conductive, and the magnetic winding coil is made of a second material that is magnetic and differs from the first material.

Abstract: A semiconductor device includes a plurality of redistribution layers, a dielectric layer, and a conductive structure. The redistribution layers are formed overlying a device die to provide an electrical connection between the device die and an external connector in a package. The dielectric layer is arranged between the redistribution layers to form a capacitor structure. The conductive structure is formed and coupled between the device die and the redistribution layers.

Abstract: A semiconductor device is disclosed. The semiconductor device includes a first die on a first substrate, a second die on a second substrate separate from the first substrate, a transmission line in a redistribution layer on a wafer, and a magnetic structure surrounds the transmission line. The first transmission line electrically connects the first die and the second die. The magnetic structure is configured to increase the characteristic impedance of the transmission line, which can save the current and power consumption of a current mirror and amplifier in a 3D IC chip-on-wafer-on-substrate (CoWoS) semiconductor package.

Abstract: A semiconductor arrangement in fan out packaging has a molding compound adjacent a side of a semiconductor die. A magnetic structure is disposed above the molding compound, above the semiconductor die, and around a transmission line coupled to an integrated circuit of the semiconductor die. The magnetic structure has a top magnetic portion, a bottom magnetic portion, a first side magnetic portion, and a second side magnetic portion. The first side magnetic portion and the second side magnetic portion are coupled to the top magnetic portion and to the bottom magnetic portion. The first side magnetic portion and the second side magnetic portion have tapered sidewalls.

Abstract: A method of forming a semiconductor device includes forming a first redistribution line on a substrate; forming a plurality of first vertical conductive structures on the first redistribution line and electrically coupled to the first redistribution line; forming a plurality of second vertical conductive structures on the substrate, wherein the first vertical conductive structures and the second vertical conductive structures are interlaced with each other, and the second vertical conductive structures are spaced apart from the first redistribution line; attaching a device die on the substrate; applying a molding compound in a molding layer overlying the substrate to surround the device die; and forming a second redistribution line on the molding layer, wherein the second redistribution line is electrically coupled to the second vertical conductive structures.

Abstract: The present disclosure relates to a semiconductor package device including a stacked antenna structure with a high-k laminated dielectric layer separating antenna and ground planes, and a method of manufacturing the structure. A semiconductor die is laterally encapsulated within an insulating structure comprising a first redistributions structure. A second redistribution structure is disposed over and electrically coupled to the first redistribution structure and the die. The second redistribution structure includes the stacked antenna structure which includes first and second conductive planes separated by a high dielectric constant laminated dielectric structure. The first conductive plane includes openings and the second conductive plane is configured to transmit and receive electromagnetic waves through the openings in the first conductive plane.

Abstract: A three-Dimensional Integrated Circuit (3DIC) Chip on Wafer on Substrate (CoWoS) packaging structure or system includes a silicon oxide interposer with no metal ingredients, and with electrically conductive TVs and RDLs. The silicon oxide interposer has a first surface and a second surface opposite to the first surface. The electrically conductive TVs penetrate through the silicon oxide interposer. The electrically interconnected RDLs are disposed over the first surface of the silicon oxide interposer, and are electrically coupled or connected to a number of the conductive TVs.

Abstract: An antenna structure includes a ground plane in a first metal layer of an integrated circuit (IC) package, a patch in a second metal layer of the IC package, a cavity structure between the ground plane and the patch, and a high-k dielectric layer between the ground plane and the patch.

Abstract: A semiconductor structure is disclosed that includes a dielectric waveguide, a first transmission electrode and a second transmission electrode, and a first receiver electrode and a second receiver electrode. The first transmission electrode and the second transmission electrode that are disposed over and below the dielectric waveguide, respectively, and the first transmission electrode and the second transmission electrode are symmetric with respect to the dielectric waveguide. The first receiver electrode and a second receiver electrode that are disposed over and below the dielectric waveguide, respectively, and the first receiver electrode and the second receiver electrode are symmetric with respect to the dielectric waveguide. The dielectric waveguide is configured to receive a transmission signal from a driver circuit through the first transmission electrode and to transmit the received transmission signal to a receiver circuit through the first receiver electrode.

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a substrate having a first side and a second side opposite to the first side; an interconnect structure disposed on the first side, the interconnect structure including a dielectric layer, and a first conductive member and a second conductive member within the dielectric layer; a waveguide disposed between the first conductive member and the second conductive member within the dielectric layer, the waveguide including a first waveguide layer, a second waveguide layer and an adhesive layer between the first waveguide layer and the second waveguide layer; a first die disposed at the first side and over the interconnect structure and electrically connected to the first conductive member; and a second die disposed at the first side and over the interconnect structure and electrically connected to the second conductive member. An associated method for fabricating the same is also disclosed.

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a polymer base layer; a backside redistribution layer (RDL) over the polymer base layer; a molding layer over the backside RDL; a polymer layer over the molding layer; a front side RDL over the polymer layer; and a metal-insulator-metal (MIM) capacitor vertically passing through the molding layer, the MIM capacitor including a first electrode, an insulation layer and a second electrode, wherein the insulation layer surrounds the first electrode, and the second electrode surrounds the insulation layer, and the molding layer surrounds the second electrode. An associated method for manufacturing a semiconductor structure is also disclosed.

Abstract: The present disclosure provides a semiconductor package device, which includes a semiconductor die and a redistribution layer disposed over and electrically coupled to the semiconductor die. The redistribution layer includes a first conductive plate, a second conductive plate disposed over the first conductive plate, an insulating film between the first conductive plate and the second conductive plate, and a first dielectric material encapsulating the first conductive plate, the second conductive plate and the insulating film. The first conductive plate and the second conductive plate are configured as an antenna plane and a ground plane, respectively.

Abstract: Among other things, a method of fabricating an integrated electronic device package is described. First trace portions of an electrically conductive trace are formed on an electrically insulating layer of a package structure, and vias of the conductive trace are formed in a sacrificial layer disposed on the electrically insulating layer. The sacrificial layer is removed, and a die is placed above the electrically insulating layer. Molding material is formed around exposed surfaces of the die and exposed surfaces of the vias, and a magnetic structure is formed within the layer of molding material. Second trace portions of the electrically conductive trace are formed above the molding material and the magnetic structure. The electrically conductive trace and the magnetic structure form an inductor. The electrically conductive trace may have a coil shape surrounding the magnetic structure. The die may be positioned between portions of the inductor.

Abstract: A semiconductor structure includes a substrate; an interconnect structure formed over the substrate and including a dielectric layer over the substrate, a first conductive member formed within the dielectric layer and a second conductive member formed within the dielectric layer; a waveguide formed between the first conductive member and the second conductive member; a first die disposed over the interconnect structure and electrically connected to the first conductive member; and a second die disposed over the interconnect structure and electrically connected to the second conductive member, wherein the waveguide is coupled with the first conductive member and the second conductive member.

Abstract: A semiconductor structure includes a dielectric waveguide, a driver die, a first transmission electrode, a second transmission electrode, and a receiver die. The driver die is configured to generate a driving signal. The first transmission electrode is located along a first side of the dielectric waveguide and configured to receive the driving signal. The second transmission electrode is located along a second side of the dielectric waveguide and electrically coupled to a transmission ground. The first transmission electrode and the second transmission electrode are mirror images. The receiver die is configured to receive a received signal from the dielectric waveguide.

Abstract: A semiconductor arrangement in fan out packaging has a molding compound adjacent a side of a semiconductor die. A magnetic structure is disposed above the molding compound, above the semiconductor die, and around a transmission line coupled to an integrated circuit of the semiconductor die. The magnetic structure has a top magnetic portion, a bottom magnetic portion, a first side magnetic portion, and a second side magnetic portion. The first side magnetic portion and the second side magnetic portion are coupled to the top magnetic portion and to the bottom magnetic portion. The first side magnetic portion and the second side magnetic portion have tapered sidewalls.