Abstract: A method of forming a semiconductor device includes forming a first redistribution line on a substrate; forming a plurality of first vertical conductive structures on the first redistribution line and electrically coupled to the first redistribution line; forming a plurality of second vertical conductive structures on the substrate, wherein the first vertical conductive structures and the second vertical conductive structures are interlaced with each other, and the second vertical conductive structures are spaced apart from the first redistribution line; attaching a device die on the substrate; applying a molding compound in a molding layer overlying the substrate to surround the device die; and forming a second redistribution line on the molding layer, wherein the second redistribution line is electrically coupled to the second vertical conductive structures.

Abstract: A semiconductor package includes a first semiconductor element, an insulating layer, and a second semiconductor element. The first semiconductor element includes at least one conductive layer and at least one via layer. The insulating layer is positioned above the first semiconductor device and includes at least one through insulator via (TIV) extending from a first side of the insulating layer to a second side of the insulating layer. The at least one TIV has a conductive core including a copper-containing material. The second semiconductor element is positioned above the insulating layer and includes at least one conductive layer and at least one via layer. The at least one TIV couples the at least one via layer of the first semiconductor element to the at least one via layer of the second semiconductor element.

Abstract: A method for forming an integrated fan-out package includes depositing an adhesive layer on a carrier, forming a back-side buffer layer over the adhesive layer, forming a back-side redistribution metal layer on the back-side buffer layer, wherein the back-side redistribution metal layer includes one or more ground plane structures, forming one or more through-insulator vias (TIVs) and one or more cavity sidewalls on the one or more ground plane structures, placing a radio frequency (RF) integrated circuit (IC) die on the back-side buffer layer, laterally encapsulating the RF IC die, the one or more TIVs, the one or more cavity sidewalls, with a molding compound, thus forming an interim substrate, wherein the cavity sidewalls and their associated ground plane structure define one or more antenna cavities, and forming a top-side redistribution (RDL) wiring structure on the interim substrate, the top-side RDL wiring structure including one or more integrated patch antenna structure, wherein the one or more integ

Abstract: A semiconductor package includes a first semiconductor element, an insulating layer, and a second semiconductor element. The first semiconductor element includes at least one conductive layer and at least one via layer. The insulating layer is positioned above the first semiconductor device and includes at least one through insulator via (TIV) extending from a first side of the insulating layer to a second side of the insulating layer. The at least one TIV has a conductive core including a copper-containing material. The second semiconductor element is positioned above the insulating layer and includes at least one conductive layer and at least one via layer. The at least one TIV couples the at least one via layer of the first semiconductor element to the at least one via layer of the second semiconductor element.

Abstract: A semiconductor device and a method are disclosed herein. The semiconductor device includes a device die, a molding layer surrounding the device die, a plurality of first vertical conductive structures formed within the molding layer, and a plurality of second vertical conductive structures formed within the molding layer. The first vertical conductive structures and the second vertical conductive structures are interlaced with each other, and an insulating structure is formed between the first vertical conductive structures and the second vertical conductive structures.

Abstract: A device includes an insulating layer disposed over a silicon substrate. The insulating layer includes a core insulating area and a peripheral insulating area. A trench laterally encloses the core insulating area and separates the core insulating area from the peripheral insulating area. A magnetic winding coil is disposed within the trench and separates the core insulating area from the peripheral insulating area. A conductive inner core is disposed within the core insulating area and is surrounded by the magnetic winding coil. The conductive inner core is made of a first material that is electrically conductive, and the magnetic winding coil is made of a second material that is magnetic and differs from the first material.

Abstract: Systems and methods are provided for an integrated chip. An integrated chip includes a package substrate including a plurality of first layers and a plurality of second layers, each second layer being disposed between a respective adjacent pair of the first layers. A transceiver unit is disposed above the package substrate. A waveguide unit including a plurality of waveguides having top and bottom walls formed in the first layers of the package substrate and sidewalls formed in the second layers of the package substrate.

Abstract: A semiconductor structure includes a dielectric waveguide, a driver die, a first transmission electrode, a second transmission electrode, and a receiver die. The driver die is configured to generate a driving signal. The first transmission electrode is located along a first side of the dielectric waveguide and configured to receive the driving signal. The second transmission electrode is located along a second side of the dielectric waveguide and electrically coupled to a transmission ground. The first transmission electrode and the second transmission electrode are mirror images. The receiver die is configured to receive a received signal from the dielectric waveguide.

Abstract: A semiconductor package includes a first semiconductor device, a second semiconductor device vertically positioned above the first semiconductor device, and a ground shielded transmission path. The ground shielded transmission path couples the first semiconductor device to the second semiconductor device. The ground shielded transmission path includes a first signal path extending longitudinally between a first end and a second end. The first signal path includes a conductive material. A first insulating layer is disposed over the signal path longitudinally between the first end and the second end. The first insulating layer includes an electrically insulating material. A ground shielding layer is disposed over the insulating material longitudinally between the first end and the second end of the signal path. The ground shielding layer includes a conductive material coupled to ground.

Abstract: A method for forming an integrated fan-out package includes depositing an adhesive layer on a carrier, forming a back-side buffer layer over the adhesive layer, forming a back-side redistribution metal layer on the back-side buffer layer, wherein the back-side redistribution metal layer includes one or more ground plane structures, forming one or more through-insulator vias (TIVs) and one or more cavity sidewalls on the one or more ground plane structures, placing a radio frequency (RF) integrated circuit (IC) die on the back-side buffer layer, laterally encapsulating the RF IC die, the one or more TIVs, the one or more cavity sidewalls, with a molding compound, thus forming an interim substrate, wherein the cavity sidewalls and their associated ground plane structure define one or more antenna cavities, and forming a top-side redistribution (RDL) wiring structure on the interim substrate, the top-side RDL wiring structure including one or more integrated patch antenna structure, wherein the one or more integ

Abstract: Methods of fabricating magnetic core inductors for an integrated voltage regulator are disclosed. In some methods, an insulating layer is attached upon a carrier layer, and the insulating layer is patterned to form a core area and a trench area. A conductive inner core is formed in the core area. A magnetic winding coil is formed in the trench area.

Abstract: A semiconductor structure and a method are disclosed herein. The semiconductor structure includes a dielectric waveguide vertically disposed between a first layer and a second layer, a driver die configured to generate, at a first output node, a driving signal, a first transmission electrode located along a first side of the dielectric waveguide and configured to receive the driving signal from the first output node, a first receiver electrode located along the first side of the dielectric waveguide, and a receiver die configured to receive a received signal from the first receiver electrode.

Abstract: A semiconductor device includes a plurality of redistribution layers, a dielectric layer, and a conductive structure. The redistribution layers are formed overlying a device die to provide an electrical connection between the device die and an external connector in a package. The dielectric layer is arranged between the redistribution layers to form a capacitor structure. The conductive structure is formed and coupled between the device die and the redistribution layers.

Abstract: An integrated fan-out package having a top-side redistribution wiring structure, a back-side redistribution wiring layer, a ground plane provided in the back-side redistribution wiring layer, and a molding compound layer having a thickness and provided between the back-side redistribution wiring layer and the top-side redistribution wiring structure is disclosed. The package has an RF IC die embedded within the molding compound layer and one or more integrated patch antenna structure provided in the top-side redistribution wiring structure. The one or more integrated patch antenna structure is coupled to the RF IC die and an antenna cavity is provided within the molding compound layer under each of the one or more integrated patch antenna.

Abstract: Glass treatment methods, wafer, panels, and semiconductor devices are disclosed. In some embodiments, a method of forming a wafer or panel includes forming an opening through a glass substrate, forming a composite film on the glass substrate and on sidewalls of the opening, and filling the opening.

Abstract: An integrated fan-out package having a top-side redistribution wiring structure, a back-side redistribution wiring layer, a ground plane provided in the back-side redistribution wiring layer, and a molding compound layer having a thickness and provided between the back-side redistribution wiring layer and the top-side redistribution wiring structure is disclosed. The package has an RF IC die embedded within the molding compound layer and one or more integrated patch antenna structure provided in the top-side redistribution wiring structure. The one or more integrated patch antenna structure is coupled to the RF IC die and an antenna cavity is provided within the molding compound layer under each of the one or more integrated patch antenna.

Abstract: A semiconductor structure and a method are disclosed herein. The semiconductor structure includes a dielectric waveguide vertically disposed between a first layer and a second layer, a driver die configured to generate, at a first output node, a driving signal, a first transmission electrode located along a first side of the dielectric waveguide and configured to receive the driving signal from the first output node, a first receiver electrode located along the first side of the dielectric waveguide, and a receiver die configured to receive a received signal from the first receiver electrode.

Abstract: A semiconductor device and a method are disclosed herein. The semiconductor device includes a device die, a molding layer surrounding the device die, a plurality of first vertical conductive structures formed within the molding layer, and a plurality of second vertical conductive structures formed within the molding layer. The first vertical conductive structures and the second vertical conductive structures are interlaced with each other, and an insulating structure is formed between the first vertical conductive structures and the second vertical conductive structures.

Abstract: Glass treatment methods, wafer, panels, and semiconductor devices are disclosed. In some embodiments, a method of forming a wafer or panel includes forming an opening through a glass substrate, forming a composite film on the glass substrate and on sidewalls of the opening, and filling the opening.

Abstract: Glass treatment methods, wafer, panels, and semiconductor devices are disclosed. In some embodiments, a method of treating a glass substrate includes forming a first film on the glass substrate, the first film having a first porosity. The method includes forming a second film on the first film, the second film comprising an electrically insulating material and having a second porosity. The first porosity is lower than the second porosity.