Patents by Inventor Wen-Tai Wang

Wen-Tai Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240036800
    Abstract: An electronic whiteboard system and an operation method thereof are provided. The electronic whiteboard system includes a data processing device. The data processing device calculates an original message amount of an original object move message according to an object move operation on a cloud electronic whiteboard operated by one of the client devices. The data processing device simulates a grouping message amount of a grouping object move message according to the object move operation. The data processing device compares the original message amount and the grouping message amount to determine whether to generate the grouping object move message, and transmits the original object move message or the grouping object move message to other of the plurality of client devices.
    Type: Application
    Filed: July 26, 2022
    Publication date: February 1, 2024
    Applicant: Optoma Corporation
    Inventors: Wen-Tai Wang, Ron-Fu Chen, Cheng-Kang Ho
  • Publication number: 20230359319
    Abstract: An electronic whiteboard system includes a data processing equipment receiving a plurality of first editing information provided by at least a portion of a plurality of client-end equipment, sorting and grouping the plurality of first editing information to select and sort from the plurality of first editing information as a plurality of pre-processing information, calculating a plurality of priority scores of the plurality of pre-processing information, sorting the plurality of pre-processing information according to the plurality of priority scores, verifying whether the plurality of pre-processing information sorted according to the priority scores are permitted to select at least one of the plurality of pre-processing information verified as permitted to generate second editing information, and executing the second editing information, so that the plurality of client-end equipment display editing results of a cloud electronic whiteboard corresponding to the second editing information.
    Type: Application
    Filed: April 27, 2023
    Publication date: November 9, 2023
    Applicant: Optoma Corporation
    Inventors: Wen-Tai Wang, Ron-Fu Chen, Cheng-Kang Ho
  • Patent number: 11569220
    Abstract: An electrostatic discharge (ESD) protection device includes a first clamping circuit, a second clamping circuit, and a diode circuit. The first clamping circuit is coupled between a first power rail and a second power rail. The second clamping circuit is coupled between a third power rail and the second power rail. The diode circuit is configured to steer an ESD current from an input/output pad to at least one of the first clamping circuit or the third power rail. The first power rail receives a first voltage, the second power rail receives a second voltage, the third power rail receives a third voltage, the third voltage is higher than the first voltage, and the first voltage is higher than the second voltage.
    Type: Grant
    Filed: December 25, 2019
    Date of Patent: January 31, 2023
    Assignees: GLOBAL UNICHIP CORPORATION, TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Wen-Tai Wang
  • Publication number: 20220417449
    Abstract: The invention relates to a multimedia system and a multimedia operation method. The multimedia system includes a first portable electronic device, a collaboration device, a camera, and an audio-visual processing device. The first portable electronic device provides a first operation instruction. The collaboration device is coupled to the first portable electronic device and receives the first operation instruction. The collaboration device provides a multimedia picture, and the multimedia picture is changed with the first operation instruction. The camera provides a video image. The audio-visual processing device is coupled to the collaboration device and the camera, and the audio-visual processing device receives the multimedia picture and a video image, and outputs a synthesized image with an immersive audio-visual effect according to the multimedia picture and the video image.
    Type: Application
    Filed: June 28, 2022
    Publication date: December 29, 2022
    Applicant: Optoma Corporation
    Inventors: Wen-Tai Wang, Sheng-Feng Chang
  • Patent number: 11527048
    Abstract: A method for simulating setting of a projector by augmented reality (AR) includes: activating an AR application on a terminal device; performing, through an image capturing element of the terminal device, dimension measurement on a space where a projector is to be disposed to obtain a space dimension; selecting a placement reference point of the projector and a display reference point of a projection picture; generating, according to the space dimension, the placement reference point, and the display reference point, a simulation picture on the terminal device when the projector projects the projection picture in the space; adjusting the projection picture and/or the projector in the simulation picture to generate an adjusted simulation picture; and comparing the adjusted simulation picture with projector parameter data of projector models to recommend at least one projector model to a user for selection or inputting, by the user, a custom projector model.
    Type: Grant
    Filed: June 22, 2021
    Date of Patent: December 13, 2022
    Assignee: Optoma Corporation
    Inventors: Wen-Tai Wang, Chi-Lin Lee, Te-Hsin Chen, Ekrem Tapan
  • Patent number: 11355490
    Abstract: A semiconductor structure corresponds to a first diode and a second diode connected in series. A first well region is on a first deep well region. Two second well regions are at two sides of the first well region respectively. A first doping region and a second doping region are on the first well region. A first isolation region is between the first doping region and the second doping region. A third well region is on a second deep well region. Two fourth well regions are at two sides of the third well region respectively. A third doping region and a fourth doping region are on the third well region. A second isolation region is between the third doping region and the fourth doping region. The second doping region and third doping region are connected. The second deep well region is separated from the first deep well region.
    Type: Grant
    Filed: November 12, 2020
    Date of Patent: June 7, 2022
    Assignees: GLOBAL UNICHIP CORPORATION, TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Yu Lin, Chun-Cheng Chen, Wen-Tai Wang
  • Publication number: 20220068908
    Abstract: A semiconductor structure corresponds to a first diode and a second diode connected in series. A first well region is on a first deep well region. Two second well regions are at two sides of the first well region respectively. A first doping region and a second doping region are on the first well region. A first isolation region is between the first doping region and the second doping region. A third well region is on a second deep well region. Two fourth well regions are at two sides of the third well region respectively. A third doping region and a fourth doping region are on the third well region. A second isolation region is between the third doping region and the fourth doping region. The second doping region and third doping region are connected. The second deep well region is separated from the first deep well region.
    Type: Application
    Filed: November 12, 2020
    Publication date: March 3, 2022
    Inventors: Chun-Yu LIN, Chun-Cheng CHEN, Wen-Tai WANG
  • Publication number: 20210407204
    Abstract: A method for simulating setting of a projector by augmented reality (AR) includes: activating an AR application on a terminal device; performing, through an image capturing element of the terminal device, dimension measurement on a space where a projector is to be disposed to obtain a space dimension; selecting a placement reference point of the projector and a display reference point of a projection picture; generating, according to the space dimension, the placement reference point, and the display reference point, a simulation picture on the terminal device when the projector projects the projection picture in the space; adjusting the projection picture and/or the projector in the simulation picture to generate an adjusted simulation picture; and comparing the adjusted simulation picture with projector parameter data of projector models to recommend at least one projector model to a user for selection or inputting, by the user, a custom projector model.
    Type: Application
    Filed: June 22, 2021
    Publication date: December 30, 2021
    Applicant: Optoma Corporation
    Inventors: Wen-Tai Wang, Chi-Lin Lee, Te-Hsin Chen, EKREM TAPAN
  • Patent number: 11037886
    Abstract: A semiconductor structure of a work unit module includes an encircling noise-resistance structure and a P-type substrate being defined with a chip region and a surrounding region surrounding the chip region. The surrounding area includes two first strip regions and two second strip regions. Each of the first strip regions is located between the second strip regions, and each of the second strip regions is located between the first strip regions. The encircling noise-resistance structure is located on the surrounding area, and includes first arrangement units and second arrangement units. The first arrangement unit is arranged in one of the first strip regions in a single row. The second arrangement unit is arranged in one of the second strip regions in a single row, and the long axis direction of the second arrangement unit is different from the long axis direction of the first arrangement unit.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: June 15, 2021
    Assignees: GLOBAL UNICHIP CORPORATION, TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Li-Ya Tseng, Wei-Cheng Yu, Bo-Yan Li, Wen-Tai Wang
  • Publication number: 20210050304
    Abstract: A semiconductor structure of a work unit module includes an encircling noise-resistance structure and a P-type substrate being defined with a chip region and a surrounding region surrounding the chip region. The surrounding area includes two first strip regions and two second strip regions. Each of the first strip regions is located between the second strip regions, and each of the second strip regions is located between the first strip regions. The encircling noise-resistance structure is located on the surrounding area, and includes first arrangement units and second arrangement units. The first arrangement unit is arranged in one of the first strip regions in a single row. The second arrangement unit is arranged in one of the second strip regions in a single row, and the long axis direction of the second arrangement unit is different from the long axis direction of the first arrangement unit.
    Type: Application
    Filed: December 6, 2019
    Publication date: February 18, 2021
    Inventors: Li-Ya TSENG, Wei-Cheng YU, Bo-Yan LI, Wen-Tai WANG
  • Publication number: 20210050341
    Abstract: An electrostatic discharge (ESD) protection device includes a first clamping circuit, a second clamping circuit, and a diode circuit. The first clamping circuit is coupled between a first power rail and a second power rail. The second clamping circuit is coupled between a third power rail and the second power rail. The diode circuit is configured to steer an ESD current from an input/output pad to at least one of the first clamping circuit or the third power rail. The first power rail receives a first voltage, the second power rail receives a second voltage, the third power rail receives a third voltage, the third voltage is higher than the first voltage, and the first voltage is higher than the second voltage.
    Type: Application
    Filed: December 25, 2019
    Publication date: February 18, 2021
    Inventor: Wen-Tai WANG
  • Patent number: 9997642
    Abstract: A diode includes a substrate, a first insulating layer, a second insulating layer, a well, a deep doped region, a first doped region, and a second doped region. The first insulating layer is disposed on the substrate. The second insulating layer is disposed on the substrate, and defines a cell region with the first insulating layer. The well is disposed on the substrate and beneath the cell region. The deep doped region is disposed in the well and beneath the cell region. The first doped region is disposed in the cell region and on the deep doped region. The second doped region is disposed adjacent to the first doped region. The second doped region is disposed on the deep doped region, and is electrically isolated from the well through the deep doped region and the first doped region.
    Type: Grant
    Filed: August 30, 2015
    Date of Patent: June 12, 2018
    Assignees: GLOBAL UNICHIP CORPORATION, TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Yu Lin, Ming-Dou Ker, Wen-Tai Wang
  • Patent number: 9748220
    Abstract: A gate-bounded silicon controlled rectifier includes a substrate, an N-type well region, a P-type well region, a first N-type semiconductor region, a first P-type semiconductor region, a second N-type semiconductor region, a second P-type semiconductor region and a third semiconductor region. The N-type well region and the P-type well region are disposed in the substrate. The first N-type semiconductor region is disposed in the N-type well region. The first P-type semiconductor region is disposed in the P-type well region. The second N-type semiconductor region is disposed in the P-type well region and located between the first N-type semiconductor region and the first P-type semiconductor region. The second P-type semiconductor region is disposed in the N-type well region and located between the first N-type semiconductor region and the first P-type semiconductor region. The third semiconductor region is located between the second N-type semiconductor region and the second P-type semiconductor region.
    Type: Grant
    Filed: January 4, 2017
    Date of Patent: August 29, 2017
    Assignees: GLOBAL UNICHIP CORPORATION, TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Yu Lin, Ming-Dou Ker, Wen-Tai Wang
  • Patent number: 9513659
    Abstract: An integrated circuit includes a main clock tree, a reference clock trunk, a reference clock buffer and a calibration circuit. The main clock tree transmits a main operation clock to an internal node via serially-coupled buffers to form a local clock at an internal node. The reference clock buffer transmits a main reference clock via the reference clock trunk to form a reference clock at a terminal node. The calibration circuit compares phases of the local clock and the reference clock to accordingly generate a control signal, so the main clock tree can adjust phase of the local clock according to the control signal.
    Type: Grant
    Filed: May 20, 2015
    Date of Patent: December 6, 2016
    Assignees: GLOBAL UNICHIP CORPORATION, TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wen-Tai Wang, Shi-Hao Chen, Ming-Jing Ho
  • Publication number: 20160329318
    Abstract: A diode includes a substrate, a first insulating layer, a second insulating layer, a well, a deep doped region, a first doped region, and a second doped region. The first insulating layer is disposed on the substrate. The second insulating layer is disposed on the substrate, and defines a cell region with the first insulating layer. The well is disposed on the substrate and beneath the cell region. The deep doped region is disposed in the well and beneath the cell region. The first doped region is disposed in the cell region and on the deep doped region. The second doped region is disposed adjacent to the first doped region. The second doped region is disposed on the deep doped region, and is electrically isolated from the well through the deep doped region and the first doped region.
    Type: Application
    Filed: August 30, 2015
    Publication date: November 10, 2016
    Inventors: Chun-Yu LIN, Ming-Dou KER, Wen-Tai WANG
  • Patent number: 9407243
    Abstract: A receiver circuit including an external terminal, a level shifter, a reset circuit, and an inverting circuit is provided. The external terminal receives the external signal. The level shifter shifts a voltage swing range of the external signal to generate a level shifting signal. The level shifter includes a pull-up unit and a pull-down unit coupled in series. The pull-up unit and the pull-down unit are alternatively switched respectively according to the external signal and the internal signal, and thus a leakage path of the level shifter is cut off for different states of the external signal. The reset circuit couples the external terminal and the level shifter and provides a reset path according to the external signal for assisting the switching of the pull-up unit and the pull-down unit. The inverting circuit couples the level shifter and inverts the level shifting signal to generate the internal signal.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: August 2, 2016
    Assignees: Global Unichip Corporation, Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wen-Tai Wang, Sheng-Tsai Huang
  • Patent number: 9343558
    Abstract: A silicon controlled rectifier includes a substrate, a well, a deep doped region, a first doped region, a second doped region, a third doped region, and a fourth doped region. The well is disposed on the substrate and underneath a cell region. The deep doped region is disposed in the well. The first doped region has a first conductivity type, and is disposed in the well. The second doped region and third doped region have the first conductivity type and are disposed on the deep doped region. The fourth doped region has a second conductivity type, and is disposed between the second doped region and the third doped region. The fourth doped region is disposed on the deep doped region, and is electrically isolated from the well through the deep doped region, the second doped region, and the third doped region.
    Type: Grant
    Filed: September 10, 2015
    Date of Patent: May 17, 2016
    Assignees: GLOBAL UNICHIP CORPORATION, TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Yu Lin, Ming-Dou Ker, Wen-Tai Wang
  • Patent number: 9281968
    Abstract: A differential circuit system is provided. The differential circuit system includes: a different circuit set including a plurality of differential circuits, a voltage regulator, and a current drainage circuit set. The differential circuits are electrically connected between a first node and a second node, and each differential circuit generates a current flowing from the first node to the second node. A high voltage is provided to the first node and a low voltage is provided to the second node. The first node receives an external voltage. According to the first voltage, the voltage regulator generates the low voltage. The low voltage is provided to the second node. The current drainage circuit set generates a drainage current in between the second node and a ground voltage. A superposed current flowing to the voltage regulator is difference of the summation of currents minus the conducting current.
    Type: Grant
    Filed: October 3, 2014
    Date of Patent: March 8, 2016
    Assignees: GLOBAL UNICHIP CORPORATION, TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Fan-Yi Jien, Wen-Tai Wang, Sheng-Tsai Huang, Yen-Cheng Chen
  • Publication number: 20150338877
    Abstract: An integrated circuit includes a main clock tree, a reference clock trunk, a reference clock buffer and a calibration circuit. The main clock tree transmits a main operation clock to an internal node via serially-coupled buffers to form a local clock at an internal node. The reference clock buffer transmits a main reference clock via the reference clock trunk to form a reference clock at a terminal node. The calibration circuit compares phases of the local clock and the reference clock to accordingly generate a control signal, so the main clock tree can adjust phase of the local clock according to the control signal.
    Type: Application
    Filed: May 20, 2015
    Publication date: November 26, 2015
    Inventors: Wen-Tai Wang, Shi-Hao Chen, Ming-Jing Ho
  • Publication number: 20150269903
    Abstract: A signal transmission circuit is provided. The signal transmission circuit includes a first driving circuit including a first differential output pair, a plurality of input/output units and a calibration module. The first differential output pair includes a positive and a negative ends. The plurality of input/output units receive a positive and a negative control signals and generate a first superimposed current at the first differential output pair. The calibration module transmits a calibration signal to the first driving circuit. The calibration module sets operation of each of the input/output unit in the first driving circuit, and generates the first superimposed current flowing to a first external resistor according to the positive and the negative control signals.
    Type: Application
    Filed: March 19, 2015
    Publication date: September 24, 2015
    Inventors: Wen-Tai Wang, Sheng-Tsai Huang, Yen-Cheng Chen