Abstract: For a multi-powered IC, an ESD protection circuit includes multiple voltage clamping circuits, each configured to provide a path for discharging an ESD transient current associated with a corresponding power supply.

Abstract: The invention provides systems and methods for ESD protection for an integrated circuit (IC) having multi-power domains. The IC comprises a first device in a first power domain having a first power line and a first ground line and a second device in a second power domain having a second power line and a second ground line. A clamp circuit having a first node and a second node is coupled to the first device and the second device to provide cross-domain protection. Alternatively, two clamp circuits are used to couple with the first device and the second device to provide cross-domain ESD protection.

Abstract: A level shifter includes a first inverter coupled between the second voltage and the first voltage, and a second inverter coupled between the second voltage and the first voltage, the second inverter being cross-coupled with the first inverter for latching a value therein. A first switch module is coupled between a first data storage node of the first and second inverters and an input signal swinging between the first voltage and a ground voltage. A second switch module is coupled between a second data storage node of the first and second inverters and an inverted input signal swinging between the ground voltage and the first voltage. The first and second inverters and the first and second switch modules include one or more MOS transistors with gate oxide layers of the same thickness.

Abstract: A level shifter includes a first inverter coupled between the second voltage and the first voltage, and a second inverter coupled between the second voltage and the first voltage, the second inverter being cross-coupled with the first inverter for latching a value therein. A first switch module is coupled between a first data storage node of the first and second inverters and an input signal swinging between the first voltage and a ground voltage. A second switch module is coupled between a second data storage node of the first and second inverters and an inverted input signal swinging between the ground voltage and the first voltage. The first and second inverters and the first and second switch modules include one or more MOS transistors with gate oxide layers of the same thickness.

Abstract: A new method to reduce switching noise on an integrated circuit device is achieved. The method comprises providing an integrated circuit device comprising a power supply, a ground, and a plurality of switchable capacitors. Each switchable capacitor is connected from the power supply to ground. The operating mode of the integrated circuit device is tracked. An optimal capacitance value is selected based on the operating mode. A set of switchable capacitors from the plurality of switchable capacitors is selected to thereby connect the optimal capacitance value from the power supply to ground.

Abstract: A receiver circuit. A reference voltage circuit is supplied with a first power supply voltage for outputting a reference voltage that is a mid-point voltage between the first power supply voltage and ground. A reference current circuit generates a first current according to the reference voltage. A receiving circuit is supplied with a second power supply voltage higher than the first power supply voltage, including a first current source for generating a second current according to the first current, and a differential amplifier circuit for generating an output signal contained within a voltage range of the first power supply voltage and centered around the mid-point voltage of the first power supply voltage according to the second current.

Abstract: A receiver circuit. A reference voltage circuit is supplied with a first power supply voltage for outputting a reference voltage that is a mid-point voltage between the first power supply voltage and ground. A reference current circuit generates a first current according to the reference voltage. A receiving circuit is supplied with a second power supply voltage higher than the first power supply voltage, including a first current source for generating a second current according to the first current, and a differential amplifier circuit for generating an output signal contained within a voltage range of the first power supply voltage and centered around the mid-point voltage of the first power supply voltage according to the second current.

Abstract: An object of the present invention is to provide a charged-device model (CDM) electrostatic discharge (ESD) protection circuit for an integrated circuit (IC). The ESD protection circuit comprises an ESD clamp device and a functional component. The ESD clamp device is coupled to a pad and a substrate having a first conductivity type. Under normal power operation, the ESD clamp device is closed. The functional component is formed on the substrate and coupled to the pad. The functional component has a first well having the first conductivity type and an isolating region having a second conductivity type for isolating the first well from the substrate. Under normal power operation, the functional component transmits signals between the IC and an external linkage. During an CDM ESD event, the CDM charges accumulated in the substrate are discharged via the ESD clamp circuit. Hence, the functional component is protected.

Abstract: A new method to reduce switching noise on an integrated circuit device is achieved. The method comprises providing an integrated circuit device comprising a power supply, a ground, and a plurality of switchable capacitors. Each switchable capacitor is connected from the power supply to ground. The operating mode of the integrated circuit device is tracked. An optimal capacitance value is selected based on the operating mode. A set of switchable capacitors from the plurality of switchable capacitors is selected to thereby connect the optimal capacitance value from the power supply to ground.

Abstract: An ESD protection component with a deep-N-well structure in CMOS technology and the relevant circuit designs are proposed in this invention. The ESD protection component comprises a lateral silicon controlled rectifier (SCR) and a deep N-well. The SCR comprises a P-type layer, an N-type layer, a first N-well and a first P-well. The P-type layer is used as an anode of the SCR; the N-type layer is used as a cathode of the SCR; the first N-well is located between the P-type layer and the N-type layer and is contacted with the P-type layer; and the first P-well is contacted to the first N-well and the N-type layer. The deep N-well is located between the first P-well and the P-substrate, and is used to isolate the electric connection between the P-substrate and the first P-well. A plurality of these ESD protection components arbitrarily connected in series increases the total holding voltage of ESD protection circuit, thus preventing occurrences of latch-up.

Abstract: A new level-shifting circuit is achieved comprising: a first cascaded switch comprising a first NMOS transistor and a first zero threshold NMOS transistor, the second cascaded switch comprises a second NMOS transistor and a second zero threshold NMOS transistor, and the cross-coupled pull-up comprises a first PMOS transistor and a second PMOS transistor. The sources of both of these PMOS transistors are coupled to a high voltage supply. The gate of the second PMOS transistor and the drain of the first PMOS transistor are coupled to the drain of the first zero threshold NMOS transistor to form an inverted output. The gate of the first PMOS transistor and the drain of the second PMOS transistor are coupled to the drain of the second zero threshold NMOS transistor to form a non-inverted output.

Abstract: Novel PMOS-bound and NMOS-bound diodes for ESD protection, together with their application circuits, are disclosed in this invention. The PMOS-bound (or NMOS bound) diode has a PMOS (or an NMOS) structure. The source/drain region enclosed by the control gate of the PMOS (or NMOS) is used as an anode (or cathode) of the PMOS-bound (or NMOS-bound) diode. The base of the PMOS (or NMOS) is used as a cathode (or anode) of the PMOS-bound (or NMOS-bound) diode. The control gate prevents any shallow trench isolation region from forming beside the p-n junction of the PMOS-bound (or NMOS-bound) diode, such that the ESD sustaining level doesn't suffer from the formation of the STI regions. Furthermore, by ensuring proper bias to the control gate during an ESD event, the turn-on speed of the PMOS-bound or NMOS-bound diode can be increased, such that the overall ESD level of an IC chip is improved.

Abstract: A power-on control circuit for an integrated circuit of the type having plural voltage source. The circuit is powered on sequentially, thereby preventing bus contention. The power-on control circuit includes a power-on detection for generating an enabling signal and disabling signal to control output buffer. When the high voltage source is powered on and the low voltage is not, the output buffer is at a high impedance state to prevent bus contention. When the low voltage is powered on after the high voltage is powered on, the output buffer is at a normal state.

Abstract: A new level shifting circuit, using a zero threshold voltage device, is described. An input swings between a low supply and ground. An output swings between a high supply and ground. An inverter has input connected to the input of the level shifting circuit and output forming an inverted level shifting input. A first NMOS transistor has the gate connected to the level shifting input and the source connected to ground. A first zero threshold NMOS transistor has the gate connected to a low bias voltage and the source connected to the first NMOS transistor drain. A first PMOS transistor has the gate connected to the level shifting output, the source connected to the high supply, and the drain connected to the first zero threshold NMOS transistor drain. A second NMOS transistor has the gate connected to the inverted level shifting input and the source connected to ground.

Abstract: A power-on control circuit for an integrated circuit of the type having plural voltage source. The circuit is powered on sequentially, thereby preventing bus contention. The power-on control circuit includes a power-on detection for generating an enabling signal and disabling signal to control output buffer. When the high voltage source is powered on and the low voltage is not, the output buffer is at a high impedance state to prevent bus contention. When the low voltage is powered on after the high voltage is powered on, the output buffer is at a normal state.

Abstract: New level shifting circuits, one using dynamic current compensation and one using dynamic voltage equalization, are described. An input swings between a low supply and ground. An output swings between a high supply and ground. An inverter input is connected to the input of the level shifting circuit to form an inverted level shifting input. A first NMOS transistor has the gate tied to the level shifting input and the source tied to ground. A first PMOS transistor has the gate tied to the level shifting output, the source tied to the high supply, and the drain tied to the first NMOS drain. A second NMOS transistor has the gate tied to the inverted level shifter input, the source tied to the ground, and the drain tied to the level shifting output. A second PMOS transistor has the gate tied to the first NMOS drain, the source tied to the high supply, and the drain is tied to the level shifting output.

Abstract: An object of the present invention is to provide a charged-device model (CDM) electrostatic discharge (ESD) protection circuit for an integrated circuit (IC). The ESD protection circuit comprises an ESD clamp device and a functional component. The ESD clamp device is coupled to a pad and a substrate having a first conductivity type. Under normal power operation, the ESD clamp device is closed. The functional component is formed on the substrate and coupled to the pad. The functional component has a first well having the first conductivity type and an isolating region having a second conductivity type for isolating the first well from the substrate. Under normal power operation, the functional component transmits signals between the IC and an external linkage. During an CDM ESD event, the CDM charges accumulated in the substrate are discharged via the ESD clamp circuit. Hence, the functional component is protected.

Abstract: New level shifting circuits, one using dynamic current compensation and one using dynamic voltage equalization, are described. An input swings between a low supply and ground. An output swings between a high supply and ground. An inverter input is connected to the input of the level shifting circuit to form an inverted level shifting input. A first NMOS transistor has the gate tied to the level shifting input and the source tied to ground. A first PMOS transistor has the gate tied to the level shifting output, the source tied to the high supply, and the drain tied to the first NMOS drain. A second NMOS transistor has the gate tied to the inverted level shifter input, the source tied to the ground, and the drain tied to the level shifting output. A second PMOS transistor has the gate tied to the first NMOS drain, the source tied to the high supply, and the drain is tied to the level shifting output.

Abstract: The present invention proposes an ESD protection circuit with low input capacitance, suitable for an I/O pad. The ESD protection circuit includes a plurality of diodes and a power-rail ESD clamp circuit between power lines. The diodes are stacked and coupled between a first power line and the I/O pad. The ESD protection circuit between power lines is coupled between the first power line and a second power line. During normal operation, the diodes are reverse-biased and the ESD protection circuit between power lines is turned off. When an ESD event between the power line and the I/O pad occurs, the diodes are forward-biased, and the ESD protection circuit between power lines is turned on to conduct ESD current. The equivalent input capacitance of the ESD protection circuit of the present invention is very small, making it particularly suitable for the I/O port of high-frequency or high-speed IC.

Abstract: An ESD protection component with a deep-N-well structure in CMOS technology and the relevant circuit designs are proposed in this invention. The ESD protection component comprises a lateral silicon controlled rectifier (SCR) and a deep N-well. The SCR comprises a P-type layer, an N-type layer, a first N-well and a first P-well. The P-type layer is used as an anode of the SCR; the N-type layer is used as a cathode of the SCR; the first N-well is located between the P-type layer and the N-type layer and is contacted with the P-type layer; and the first P-well is contacted to the first N-well and the N-type layer. The deep N-well is located between the first P-well and the P-substrate, and is used to isolate the electric connection between the P-substrate and the first P-well. A plurality of these ESD protection components arbitrarily connected in series increases the total holding voltage of ESD protection circuit, thus preventing occurrences of latch-up.