Abstract: A semiconductor structure according to the present disclosure includes a first memory array in a first cache and a second memory array in a second cache. The first memory array includes a plurality of first memory cells arranged in M1 rows and N1 columns. The second memory array includes a plurality of second memory cells arranged in M2 rows and N2 columns. The semiconductor structure also includes a first bit line coupled to a number of N1 first memory cells in one of the M1 rows, and a second bit line coupled to a number of N2 second memory cells in one of the M2 rows. N1 is smaller than N2, and a width of the first bit line is smaller than a width of the second bit line.

Abstract: Provided are a memory structure and a manufacturing method thereof. The memory structure includes first and second gates, a dielectric hump, a first spacer, a charge storage layer, a gate dielectric layer, a high-k layer and doped regions. The first and the second gates are disposed on a substrate. The dielectric hump is disposed on the substrate between the first gate and the second gate. The first spacer is disposed on a sidewall of the dielectric hump. The charge storage layer is disposed between the first gate and the substrate. The gate dielectric layer is disposed between the second gate and the substrate. The high-k layer is disposed between the first gate and the charge storage layer and between the second gate and the gate dielectric layer. The doped regions are disposed in the substrate at two sides of the first gate and at two sides of the second gate.

Abstract: A method and device for identifying the washing quality of a feather material are applied to a feather material washing apparatus and essentially entail: a sampling unit that takes an appropriate amount of the water discharged from the feather material washing apparatus as a water sample, an impurity removing module that removes feather fiber and impurities that may compromise inspection accuracy, and a laser sensing device that senses, while the water sample is static, a transparency value of a portion of the water sample that extends across a predetermined distance, in order to identify the washing quality of a washed feather material. The method and device for identifying the washing quality of a feather material exercise intelligent judgment to enable a consistent standard, to ensure the efficiency and quality of a feather material washing procedure, and to reduce the associated costs.

Abstract: One aspect of the present disclosure pertains to a semiconductor device. The semiconductor device includes a semiconductor substrate and a transistor formed over the semiconductor substrate. The transistor includes a first source/drain (S/D) feature, a second S/D feature, a channel region interposed between the first and second S/D features, and a gate stack engaging the channel region. The semiconductor device includes a first S/D contact landing on a top surface of the first S/D feature, a second S/D contact landing on a top surface of the second S/D feature, and a dielectric plug penetrating through the semiconductor substrate and landing on a bottom surface of the first S/D feature. The dielectric plug spans a width equal to or smaller than a width of the first S/D feature.

Abstract: A camera apparatus includes a bearing member, a first drive assembly, a camera module, a rotating member, and a lifting member. The first drive assembly is mounted on the bearing member, and the rotating member is rotatably disposed on the bearing member. The first drive assembly fits the rotating member, the rotating member fits the lifting member, and the rotating member is configured to drive the lifting member to ascend or descend during rotation. The camera module includes a camera and a second drive assembly, the second drive assembly is connected to the camera, and the second drive assembly is configured to drive the camera to ascend or descend.

Abstract: An electric valve/door, and a control apparatus and method thereof are provided. The electric valve/door includes a control apparatus. The control apparatus includes an alternating current (AC) asynchronous motor, a transmission device, and a valve driver. The valve driver is connected to the AC asynchronous motor. The AC asynchronous motor is connected to the valve/door through the transmission device. The valve driver is configured to collect information of a real-time torque of the AC asynchronous motor or the valve/door during operation, and take a set torque of the valve driver as an input and the real-time torque as a feedback to immediately correct an output torque of the valve driver or a limit value of the output torque by using a proportional-integral-derivative (PID) control algorithm, to meet requirements for response speed and control precision of each stage in opening and closing processes of the valve/door.

Abstract: A cushion package box includes a box body, a first cushion member and a plurality of paper tubes. The first cushion member is disposed in the box body and the first cushion member has a porous structure. The plurality of paper tubes is disposed in the box body. At least one of the plurality of paper tubes is in contact with the first cushion member. An opening direction of the porous structure is different from an opening direction of the at least one paper tube.

Abstract: An electric valve/door, and a control apparatus and method thereof are provided. The electric valve/door includes a control apparatus. The control apparatus includes an alternating current (AC) asynchronous motor, a transmission device, and a valve driver. The valve driver is connected to the AC asynchronous motor. The AC asynchronous motor is connected to the valve/door through the transmission device. The valve driver is configured to collect information of a real-time torque of the AC asynchronous motor or the valve/door during operation, and take a set torque of the valve driver as an input and the real-time torque as a feedback to immediately correct an output torque of the valve driver or a limit value of the output torque by using a proportional-integral-derivative (PID) control algorithm, to meet requirements for response speed and control precision of each stage in opening and closing processes of the valve/door.

Abstract: A method for forming a high electron mobility transistor includes the steps of providing a substrate, forming a channel layer, a barrier layer, and a first passivation layer sequentially on the substrate, forming a plurality of trenches through at least a portion of the first passivation layer, forming a second passivation layer on the first passivation layer and covering along sidewalls and bottom surfaces of the trenches, and forming a conductive plate structure on the second passivation layer and filling the trenches.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip comprising a memory cell. The memory cell is disposed within a dielectric structure that overlies a substrate. The memory cell comprises a data storage structure disposed between a bottom electrode and a top electrode. An upper conductive structure is disposed in the dielectric structure and on the top electrode. The upper conductive structure comprises a protrusion disposed below an upper surface of the top electrode. A sidewall spacer structure is disposed around the memory cell. The sidewall spacer structure comprises a first sidewall spacer layer around the data storage structure and a second sidewall spacer layer abutting the first sidewall spacer layer. The protrusion contacts the second sidewall spacer layer.

Abstract: The invention relates to a light emitting diode, which comprises a substrate and a semiconductor epitaxy structure. The semiconductor epitaxial structure is disposed on the substrate. The semiconductor epitaxial structure comprises semiconductor composite layers and a plurality of current spreading layers which are disposed among the semiconductor composite layers. The doping concentrations of the upper and lower adjacent current spreading layers are alternately high and low.

Abstract: Implementations described herein provide a method of forming a semiconductor device. The method includes forming a nanostructure having a first set of layers of a first material and a second set of layers, alternating with the first set of layers, having a second material. The method further includes depositing a hard mask on a top layer of the first set of layers, the hard mask including a first hard mask layer on the top layer of the first set of layers and a second hard mask layer on the first hard mask layer. The method also includes depositing elements of a cladding structure on sidewalls of the nanostructure and the hard mask. The method further includes removing a top portion of the cladding structure. The method further includes removing the second hard mask layer after removing the top portion of the cladding structure.

Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a magnetic tunnel junction (MTJ) region and an edge region, forming an first inter-metal dielectric (IMD) layer on the substrate, and then forming a first MTJ and a second MTJ on the first IMD layer, in which the first MTJ is disposed on the MTJ region while the second MTJ is disposed on the edge region. Next, a second IMD layer is formed on the first MTJ and the second MTJ.

Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.

Abstract: Provided are a method and apparatus for analyzing a laying stress on a cable. The method for analyzing a laying stress on a cable includes: segmenting, according to cable grounding manners, cable laying manners and cable bending types that correspond to the discrete points of pipeline detection in a cable laying channel, the discrete points; and performing, according to segmentation information and measurement information of the discrete points, stress analysis calculation on minimum segments in which the discrete points are located. In the present application, stress analysis of each segment of the cable during the cable laying process is achieved in real time, providing data support for laying the cable. Workers responsible for laying the cable can adopt corresponding protective measures during the laying process according to a stress analysis result so that the cable can be really protected, improving the safety of the cable during the cable laying process.

Abstract: This disclosure provides systems, methods, and devices for image processing that support enhanced variable aperture (VA) camera operations. In a first aspect, a method of image processing includes determining first image statistics for first image data representing a first scene captured at a first aperture; and determining whether the first image data satisfies a first criteria. When the first image data satisfies the first criteria, the image processing includes determining an updated lens shading correction (LSC) corresponding to the first aperture based on the first image statistics and on a current LSC corresponding to the first aperture; and determining a first output image frame based on the updated LSC and the first image data. Other aspects and features are also claimed and described.

Abstract: Embodiments of this application mainly relate to the field of data processing technologies, and in particular, to microservice orchestration methods and apparatus, electronic devices, and readable media. A first node is established in a first runtime for each of a plurality of microservices. The first node is configured to control execution of the microservice. Construction performed by a user on a behavior tree is received. The behavior tree includes a leaf node, and the leaf node represents the microservice. The behavior tree is parsed, where the leaf node is mapped to the first node. An instance of the behavior tree is generated.

Abstract: Provided are a memory structure and a manufacturing method thereof. The memory structure includes a substrate having first and second regions, first and second isolation structures in the substrate, a charge storage layer on the substrate, first and second gates and doped regions. The first isolation structures define first active areas in the first region. A top surface of the first isolation structure is higher than that of the substrate. The second isolation structures define second active areas in the second region. A top surface of the second isolation structure is lower than that of the substrate. The first gate is on the charge storage layer in the first active area. The second gate is on the charge storage layer in the second active area. The doped regions are in the substrate at two sides of the first gate and at two sides of the second gate.

Abstract: An optical device includes a range finding module. The range finding module includes a first light condenser unit, a light emitting unit and a light receiving unit. The first light condenser unit defines an optical axis and a hole disposed along the optical axis. The first light condenser unit, the light emitting unit and the light receiving unit are sequentially arranged along the optical axis. The light is emitted by the light emitting unit, passes through the hole, reaches an object, is reflected by the object, is converged by the first light condenser unit and is received by the light receiving unit to generate an electrical signal.

Abstract: A structured-light three-dimensional (3D) scanning system includes a projector that emits a projected light with a predetermined pattern onto an object; an image capture device that generates a captured image according to a reflected light reflected from the object, the predetermined pattern of the projected light being distorted due to 3D shape of the object, thereby resulting in a distorted pattern; a depth decoder that converts the distorted pattern into a depth map representing the 3D shape of the object; and a depth fusion device that generates a fused depth map according to at least two different depth maps associated with the object.