Abstract: The invention relates to a light emitting diode, which comprises a substrate and a semiconductor epitaxy structure. The semiconductor epitaxial structure is disposed on the substrate. The semiconductor epitaxial structure comprises semiconductor composite layers and a plurality of current spreading layers which are disposed among the semiconductor composite layers. The doping concentrations of the upper and lower adjacent current spreading layers are alternately high and low.

Abstract: Provided are a memory structure and a manufacturing method thereof. The memory structure includes a substrate having first and second regions, first and second isolation structures in the substrate, a charge storage layer on the substrate, first and second gates and doped regions. The first isolation structures define first active areas in the first region. A top surface of the first isolation structure is higher than that of the substrate. The second isolation structures define second active areas in the second region. A top surface of the second isolation structure is lower than that of the substrate. The first gate is on the charge storage layer in the first active area. The second gate is on the charge storage layer in the second active area. The doped regions are in the substrate at two sides of the first gate and at two sides of the second gate.

Abstract: Implementations described herein provide a method of forming a semiconductor device. The method includes forming a nanostructure having a first set of layers of a first material and a second set of layers, alternating with the first set of layers, having a second material. The method further includes depositing a hard mask on a top layer of the first set of layers, the hard mask including a first hard mask layer on the top layer of the first set of layers and a second hard mask layer on the first hard mask layer. The method also includes depositing elements of a cladding structure on sidewalls of the nanostructure and the hard mask. The method further includes removing a top portion of the cladding structure. The method further includes removing the second hard mask layer after removing the top portion of the cladding structure.

Abstract: Embodiments of this application mainly relate to the field of data processing technologies, and in particular, to microservice orchestration methods and apparatus, electronic devices, and readable media. A first node is established in a first runtime for each of a plurality of microservices. The first node is configured to control execution of the microservice. Construction performed by a user on a behavior tree is received. The behavior tree includes a leaf node, and the leaf node represents the microservice. The behavior tree is parsed, where the leaf node is mapped to the first node. An instance of the behavior tree is generated.

Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.

Abstract: Provided are a method and apparatus for analyzing a laying stress on a cable. The method for analyzing a laying stress on a cable includes: segmenting, according to cable grounding manners, cable laying manners and cable bending types that correspond to the discrete points of pipeline detection in a cable laying channel, the discrete points; and performing, according to segmentation information and measurement information of the discrete points, stress analysis calculation on minimum segments in which the discrete points are located. In the present application, stress analysis of each segment of the cable during the cable laying process is achieved in real time, providing data support for laying the cable. Workers responsible for laying the cable can adopt corresponding protective measures during the laying process according to a stress analysis result so that the cable can be really protected, improving the safety of the cable during the cable laying process.

Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a magnetic tunnel junction (MTJ) region and an edge region, forming an first inter-metal dielectric (IMD) layer on the substrate, and then forming a first MTJ and a second MTJ on the first IMD layer, in which the first MTJ is disposed on the MTJ region while the second MTJ is disposed on the edge region. Next, a second IMD layer is formed on the first MTJ and the second MTJ.

Abstract: This disclosure provides systems, methods, and devices for image processing that support enhanced variable aperture (VA) camera operations. In a first aspect, a method of image processing includes determining first image statistics for first image data representing a first scene captured at a first aperture; and determining whether the first image data satisfies a first criteria. When the first image data satisfies the first criteria, the image processing includes determining an updated lens shading correction (LSC) corresponding to the first aperture based on the first image statistics and on a current LSC corresponding to the first aperture; and determining a first output image frame based on the updated LSC and the first image data. Other aspects and features are also claimed and described.

Abstract: An optical device includes a range finding module. The range finding module includes a first light condenser unit, a light emitting unit and a light receiving unit. The first light condenser unit defines an optical axis and a hole disposed along the optical axis. The first light condenser unit, the light emitting unit and the light receiving unit are sequentially arranged along the optical axis. The light is emitted by the light emitting unit, passes through the hole, reaches an object, is reflected by the object, is converged by the first light condenser unit and is received by the light receiving unit to generate an electrical signal.

Abstract: An interconnect fabrication method is disclosed herein that utilizes a disposable etch stop hard mask over a gate structure during source/drain contact formation and replaces the disposable etch stop hard mask with a dielectric feature (in some embodiments, dielectric layers having a lower dielectric constant than a dielectric constant of dielectric layers of the disposable etch stop hard mask) before gate contact formation. An exemplary device includes a contact etch stop layer (CESL) having a first sidewall CESL portion and a second sidewall CESL portion separated by a spacing and a dielectric feature disposed over a gate structure, where the dielectric feature and the gate structure fill the spacing between the first sidewall CESL portion and the second sidewall CESL portion. The dielectric feature includes a bulk dielectric over a dielectric liner. The dielectric liner separates the bulk dielectric from the gate structure and the CESL.

Abstract: The present disclosure relates to a semiconductor device and its manufacturing method, and the semiconductor device includes a substrate, a channel layer, a gate electrode, a first electrode, a second electrode, and a metal plate. The channel layer is disposed on the substrate, and the gate electrode is disposed on the channel layer. The first electrode and the second electrode are disposed on the channel layer, at two opposite sides of the gate electrode respectively. The metal plate is disposed over the channel layer, between the first electrode and the gate electrode. The metal plate includes a first extending portion and a second extending portion, wherein the second extending portion extends towards the substrate without contacting the channel layer, and the first extending portion extends toward and directly contacts the first electrode or the second electrode.

Abstract: A three-dimensional structure sensing system includes an image sensor that receives a reflected light from an object irradiated by an emitted light, the reflected light being converted into image data representing an image of the object; and a depth processing unit that generates depth data according to the image data. It is determined whether the depth data is affected by a reflective surface according to the image data and the depth data.

Abstract: A structured-light three-dimensional (3D) scanning system includes a projector that emits a projected light with a predetermined pattern onto an object; an image capture device that generates a captured image according to a reflected light reflected from the object, the predetermined pattern of the projected light being distorted due to 3D shape of the object, thereby resulting in a distorted pattern; a depth decoder that converts the distorted pattern into a depth map representing the 3D shape of the object; and a depth fusion device that generates a fused depth map according to at least two different depth maps associated with the object.

Abstract: The present disclosure relates generally to topical delivery compositions for improved topical composition comprising at least one active agent, at least one phospholipid and urea. The active agent of the present disclosure comprises non-steroid anti-inflammatory drugs (NSAIDs). The topical delivery compositions of the present disclosure improve the solubility of the NSAIDs. The present disclosure also relates to a method for preparation of a topical composition of the present disclosure. The topical compositions are useful in treating inflammation, arthritis and/or pain, or conditions for which the signs and symptoms include inflammation, arthritis and/or pain, by topical administration to a subject.

Abstract: A method of manufacturing a semiconductor structure is provided. A substrate including a first silicon carbide layer and a second silicon carbide layer under the first silicon carbide layer is formed. The substrate includes a unit region and a termination region surrounding the unit region. A first guard ring structure is formed in the termination region and the first silicon carbide layer, adjoining a top surface of the first silicon carbide layer. A second guard ring structure is formed in the termination region and the second silicon carbide layer. Second guard ring well regions of the second guard ring structure correspond one-on-one to first guard ring well regions of the first guard ring structure. Each of the second guard ring well regions overlaps with a corresponding one of the first guard ring well regions in a vertical direction perpendicular to the top surface of the substrate.

Abstract: A frequency locked loop circuit, comprising an operational circuit, a first impedance circuit, a second impedance circuit, a switching circuit and a frequency generation circuit. The operational circuit is configured to output an operational signal according to a voltage difference between a positive terminal and a negative terminal. The switching circuit is configured to periodically conduct the negative terminal to one of the first impedance node and the second impedance node, and periodically conduct the positive terminal to the other one of the first impedance node and the second impedance node. The frequency generation circuit is configured to periodically sample the operational signal to generate a sample signal to generate a clock signal. An operational frequency of the operational signal is an integer multiple of a sampling frequency of the frequency generation circuit.

Abstract: Various methods for manufacturing semiconductor structures are provided. An embodiment method includes forming a first patterned hard mask and epitaxial layer on a semiconductor substrate, and forming a first doped region in the epitaxial layer by performing a first implantation through the first patterned hard mask. A second doped region is formed in the epitaxial layer by performing a second implantation through the first patterned hard mask, with the first doped region at least partially overlapping the second doped region. A second patterned hard mask is formed, which surrounds the first patterned hard mask and covers at least a portion of the first doped region. A third doped region is formed in the epitaxial layer by performing a third implantation through the first patterned hard mask and the second patterned hard mask.

Abstract: A system may include a memory and a processor in communication with the memory. The processor may be configured to perform operations. The operations may include calculating a priority factor with a node autonomous center in a node and computing a node service capability with the node autonomous center. The operations may further include selecting, with the node autonomous center, a task based on the priority factor and the node service capability. The operations may further include directing the task to the node.

Abstract: A spatial light modulator device includes an array of spatial light modulator cells located over a substrate. Each of the spatial light modulator cells includes: a layer stack including a phase change material plate, a spacer dielectric material plate that underlies the phase change material plate, and a metallic heater plate underlying the spacer dielectric material plate and including outer sidewalls; and a pair of bottom electrode via structures contacting a respective surface segment of a bottom surface of the metallic heater plate. Each of the outer sidewalls of the metallic heater plate is vertically coincident with a respective sidewall of the spacer dielectric material plate and with a respective sidewall of the phase change material plate.

Abstract: A time series anomaly detection method, system, and computer program product that processes time series data includes absorbing profiles of the time series data and anomaly types of a model as features, optimizing biased ranks to create optimized ranks through merging initial ranks with new ranks generated by real anomalies, and auto-suggesting the optimized ranks for saving a predetermined amount of data operation.