Abstract: In various aspects, the present disclosure is directed to methods and compositions for the simultaneous production of carbon nanotubes and hydrogen gas from lower hydrocarbon comprises methane, ethane, propane, butane, or a combination thereof utilizing the disclosed catalysts. In various aspects, the disclosure relates to methods for COx-free production of hydrogen with concomitant production of carbon nanotubes. Also disclosed are methods and compostions for selective base grown carbon nanotubes over a disclosed catalyst composition. In a further aspect, the disclosure relates to mono, bimetallic, and trimetallic catalysts comprising a 3d transition metal (e.g., Ni, Fe, Co, Mn, Cr, Mo, and combinations thereof) over a support material selected from a silica, an alumina, a zeolite, titanium dioxide, and combinations thereof. This abstract is intended as a scanning tool for purposes of searching in the particular art and is not intended to be limiting of the present disclosure.

Abstract: A depth sensing system and a depth sensing method are provided. The sensing system includes depth sensing module and a processor for performing the sensing method. The depth sensing method incudes: obtaining a sensed target data set via a depth sensing module; calculating a period number corresponding to a measuring pixel; and calculating an actual range value or an actual depth of the measuring pixel in accordance with a period number and a range value of the measuring pixel. The step of calculating the period number of the target data set includes: calculating a spatial ratio in accordance with the position values of the pixel of optical center and measuring pixel, and a focal length of the depth sensing module; calculating a basic range in accordance with the spatial ratio and an unit depth; and calculating the period number corresponding to the measuring pixel.

Abstract: A multi-functional reconfigurable intelligence surface (MF-RIS) integrating signal reflection, refraction and amplification and energy harvesting and an application thereof are provided. The MF-RIS can support wireless signal reflection, refraction and amplification and energy harvesting on one surface, to amplify, reflect, or refract a signal through harvested energy, and further enhance effective coverage of wireless signals. When a signal model of the MF-RIS constructed in the present disclosure is applied to a multi-user wireless network, a non-convex optimization problem of jointly designing operation modes and parameters that include BS transmit beamforming, and different components and a deployment position of the MF-RIS is constructed with an objective of maximizing a sum rate (SR) of a plurality of users in an MF-RIS-assisted non-orthogonal multiple access network.

Abstract: The device includes a projecting device, an image sensor and a computing circuit. The projecting device provides a light beam having a predetermined pattern that is projected onto an object. The image sensor receives the light beam reflected from the object to generate an image. The computing circuit compares the image with a first ground-truth image and a ground-truth image to generate a first depth value and a second depth value respectively. The first and second depth values are combined to generate a depth result.

Abstract: The present disclosure relates to an antibody or antigen-binding fragment thereof that specifically binds to a spike protein of SARS-CoV-2. The present disclosure also relates to a pharmaceutical composition, a method for treating and/or preventing diseases and/or disorders caused by a coronavirus in a subject in need thereof, and a method for detecting a coronavirus in a sample.

Abstract: Embodiments of this disclosure provide a method and an apparatus for handling a protocol data unit session, and an electronic device. The method includes: transmitting a protocol data unit PDU session release request to a network device in a case that at least one of an authorized quality of service QoS rule, packet filter, and/or authorized QoS flow description configured by a network device for the PDU session exceeds a maximum support capability set by user equipment for the PDU session.

Abstract: A memory operation method, comprising: when a first super block of a memory device is a open block (or in programming state), obtaining a first read count of one of a plurality of first memory blocks in the first super block, wherein the first read count is a number of times that data of one of the first memory blocks is read out; determining whether the first read count is larger than a first threshold; and when the first read count is larger than the first threshold, moving a part of the data in the first super block to a safe area in the memory device, wherein the part of the data comprises data in the first memory block.

Abstract: A food status recognition and display system and a food status recognition and display method are provided. The food status recognition and display system includes a camera and light source module, a processing module and a display interface. The camera and light source module faces a food storage environment. After the camera and light source module photographs at least one food item using the light beams in a visible light band, a near-infrared light band and a short-wave infrared light band, respective food photography results are obtained. The processing module receives the food photography results. After the food photography results are processed through an image recognition process, a vegetation index formula, a vegetation water content formula and a vegetation correlation analysis formula, at least one corresponding food status information is generated and then transmitted.

Abstract: Electrical plugs may include a first conductive pin and a second conductive pin extending from a base structure. A first insulating sleeve may surround a first base portion of the first pin and a second insulating sleeve may surround a second base portion of the second pin. Each of the first insulating sleeve and the second insulating sleeve may have a wall thickness of between about 0.10 mm and about 0.30 mm. Various other related devices, systems, and methods are also disclosed.

Abstract: Sacrificial pillars for a semiconductor device assembly, and associated methods and systems are disclosed. In one embodiment, a region of a semiconductor die may be identified to include sacrificial pillars that are not connected to bond pads of the semiconductor die, in addition to live conductive pillars connected to the bond pads. The region with the sacrificial pillars, when disposed in proximity to the live conductive pillars, may prevent an areal density of the live conductive pillars from experiencing an abrupt change that may result in intolerable variations in heights of the live conductive pillars. As such, the sacrificial pillars may improve a coplanarity of the live conductive pillars by reducing variations in the heights of the live conductive pillars. Thereafter, the sacrificial pillars may be removed from the semiconductor die.

Abstract: A compound of formula I, a pharmaceutically acceptable salt thereof, or a solvent compound, an enantiomer, a diastereomer or a tautomer of the compound or a pharmaceutically acceptable salt thereof is disclosed. The 3H-imidazo[4,5-C]pyridine pleuromutilin onium salt derivatives exhibit good water solubility and excellent activity against resistant mycoplasma, in vivo and in vitro antibacterial activity, and are of great value in the development of anti-resistant bacteria drugs and have good medical application prospects.

Abstract: An IC device includes first and second power rails extending in a first direction and carrying one of a power supply or reference voltage, a third power rail extending between the first and second power rails and carrying the other of the power supply or reference voltage, and a plurality of transistors including first through fourth active areas extending between the first and second power rails, a plurality of gate structures extending perpendicularly to the first direction, and first and second conductive segments extending in the second direction across the third power rail. Each of the second and third active areas is adjacent to the third power rail, each of the first and second conductive segments is electrically connected to S/D structures in each of the second and third active areas, and the plurality of transistors is configured as one of an AOI, an OAI, or a four-input NAND gate.

Abstract: A method and device for identifying the washing quality of a feather material are applied to a feather material washing apparatus and essentially entail: a sampling unit that takes an appropriate amount of the water discharged from the feather material washing apparatus as a water sample, an impurity removing module that removes feather fiber and impurities that may compromise inspection accuracy, and a laser sensing device that senses, while the water sample is static, a transparency value of a portion of the water sample that extends across a predetermined distance, in order to identify the washing quality of a washed feather material. The method and device for identifying the washing quality of a feather material exercise intelligent judgment to enable a consistent standard, to ensure the efficiency and quality of a feather material washing procedure, and to reduce the associated costs.

Abstract: Provided are a memory structure and a manufacturing method thereof. The memory structure includes first and second gates, a dielectric hump, a first spacer, a charge storage layer, a gate dielectric layer, a high-k layer and doped regions. The first and the second gates are disposed on a substrate. The dielectric hump is disposed on the substrate between the first gate and the second gate. The first spacer is disposed on a sidewall of the dielectric hump. The charge storage layer is disposed between the first gate and the substrate. The gate dielectric layer is disposed between the second gate and the substrate. The high-k layer is disposed between the first gate and the charge storage layer and between the second gate and the gate dielectric layer. The doped regions are disposed in the substrate at two sides of the first gate and at two sides of the second gate.

Abstract: A method for forming a high electron mobility transistor includes the steps of providing a substrate, forming a channel layer, a barrier layer, and a first passivation layer sequentially on the substrate, forming a plurality of trenches through at least a portion of the first passivation layer, forming a second passivation layer on the first passivation layer and covering along sidewalls and bottom surfaces of the trenches, and forming a conductive plate structure on the second passivation layer and filling the trenches.

Abstract: The invention relates to a light emitting diode, which comprises a substrate and a semiconductor epitaxy structure. The semiconductor epitaxial structure is disposed on the substrate. The semiconductor epitaxial structure comprises semiconductor composite layers and a plurality of current spreading layers which are disposed among the semiconductor composite layers. The doping concentrations of the upper and lower adjacent current spreading layers are alternately high and low.

Abstract: Embodiments of this application mainly relate to the field of data processing technologies, and in particular, to microservice orchestration methods and apparatus, electronic devices, and readable media. A first node is established in a first runtime for each of a plurality of microservices. The first node is configured to control execution of the microservice. Construction performed by a user on a behavior tree is received. The behavior tree includes a leaf node, and the leaf node represents the microservice. The behavior tree is parsed, where the leaf node is mapped to the first node. An instance of the behavior tree is generated.

Abstract: Provided are a memory structure and a manufacturing method thereof. The memory structure includes a substrate having first and second regions, first and second isolation structures in the substrate, a charge storage layer on the substrate, first and second gates and doped regions. The first isolation structures define first active areas in the first region. A top surface of the first isolation structure is higher than that of the substrate. The second isolation structures define second active areas in the second region. A top surface of the second isolation structure is lower than that of the substrate. The first gate is on the charge storage layer in the first active area. The second gate is on the charge storage layer in the second active area. The doped regions are in the substrate at two sides of the first gate and at two sides of the second gate.

Abstract: Implementations described herein provide a method of forming a semiconductor device. The method includes forming a nanostructure having a first set of layers of a first material and a second set of layers, alternating with the first set of layers, having a second material. The method further includes depositing a hard mask on a top layer of the first set of layers, the hard mask including a first hard mask layer on the top layer of the first set of layers and a second hard mask layer on the first hard mask layer. The method also includes depositing elements of a cladding structure on sidewalls of the nanostructure and the hard mask. The method further includes removing a top portion of the cladding structure. The method further includes removing the second hard mask layer after removing the top portion of the cladding structure.

Abstract: A three-dimensional structure sensing system includes an image sensor that receives a reflected light from an object irradiated by an emitted light, the reflected light being converted into image data representing an image of the object; and a depth processing unit that generates depth data according to the image data. It is determined whether the depth data is affected by a reflective surface according to the image data and the depth data.