Abstract: A digital computer includes a plurality of processing elements, a command processor, a diagnostic processor and a communications network. The processing elements each performs data processing and data communications operations in connection with commands. The processing elements also performing diagnostic operations in response to diagnostic operation requests and providing diagnostic results in response thereto. The command processor generates commands for the processing elements, and also performs diagnostic operations in response to diagnostic operation requests and providing diagnostic results in response thereto. The diagnostic processor generates diagnostic requests. The communication network includes three elements, including a data router, a control network and a diagnostic network. The data router is connected to the processing elements for facilitating the transfer of data among them during a data communications operation.

Abstract: A parallel computer comprising a plurality of processors and an interconnection network for transferring messages among the processors. At least one of the processors, as a source processor, generates messages, each including an address defining a path through the interconnection network from the source processor to one or more of the processors which are to receive the message as destination processors. The interconnection network establishes, in response to a message from the source processor, a path in accordance with the address from the source processor in a downstream direction to the destination processors thereby to facilitate transfer of the message to the destination processors. Each destination processor generates response indicia in response to a message. The interconnection network receives the response indicia from the destination processor(s) and generates, in response, consolidated response indicia which it transfers in an upstream direction to the source processor.

Abstract: A clock buffer circuit that generates a local clock signal in response to a system clock signal. The clock buffer circuit includes a buffer circuit for generating the local clock signal in response to an intermediate clock signal. A buffer control circuit generates the intermediate clock signal in response to the system clock signal and the local clock signal. The buffer control circuit provides a variable delay so that, with an additional delay provided by the buffer circuit, the local clock signal has a selected phase relationship in relation to the system clock signal.

Abstract: An improvement is made to continuous chip fryers by introducing means of control to the flow of oil in the fryer. The disclosure is most applicable to the type of fryers where heat is added externally in a separate heat exchanger. The controlled oil flow allows an increased loading of the fryer, thus reducing equipment size and oil resident time.

Abstract: A convection oven being an air distribution chamber above the main cooking compartment is the subject of the present invention. A centrifugal fan draws air from the cooking compartment into the air chamber and directs the air outwardly past an electrical heating element mounted within the air chamber in a serpentine configuration. The heated air passes from the air chamber into the cooking compartment through a series of slots which are arranged in a non-symmetrical pattern in order to heat the cooking compartment uniformly for uniform cooking of the food.