Abstract: Various embodiments of the present disclosure are directed towards a method for forming a varactor comprising a reduced surface field (RESURF) region. The method includes forming a drift region having a first doping type within a substrate. A RESURF region having a second doping type is formed within the substrate such that the RESURF region is below the drift region. A gate structure is formed on the substrate. A pair of contact regions is formed within the substrate on opposing sides of the gate structure. The contact regions respectively abut the drift region and have the first doping type, and wherein the first doping type is opposite the second doping type.

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first interconnect dielectric layer arranged over a substrate. An interconnect wire extends through the first interconnect dielectric layer, and a barrier structure is arranged directly over the interconnect wire. The integrated chip further includes an etch stop layer arranged over the barrier structure and surrounds outer sidewalls of the barrier structure. A second interconnect dielectric layer is arranged over the etch stop layer, and an interconnect via extends through the second interconnect dielectric layer, the etch stop layer, and the barrier structure to contact the interconnect wire.

Abstract: A method of forming a semiconductor device structure is provided. The method includes forming a masking structure with first openings over a semiconductor substrate and correspondingly forming metal layers in the first openings. The method also includes recessing the masking structure to form second openings between the metal layers and forming a sacrificial layer surrounded by a first liner in each of the second openings. In addition, after forming a second liner over the sacrificial layer in each of the second openings, the method includes removing the sacrificial layer in each of the second openings to form a plurality of air gaps therefrom.

Abstract: A semiconductor light-emitting device includes a semiconductor stack including a first semiconductor layer and a second semiconductor layer; a first reflective layer formed on the first semiconductor layer and including a plurality of vias; a plurality of contact structures respectively filled in the vias and electrically connected to the first semiconductor layer; a second reflective layer including metal material formed on the first reflective layer and contacting the contact structures; a plurality of conductive vias surrounded by the semiconductor stack; a connecting layer formed in the conductive vias and electrically connected to the second semiconductor layer; a first pad portion electrically connected to the second semiconductor layer; and a second pad portion electrically connected to the first semiconductor layer, wherein a shortest distance between two of the conductive vias is larger than a shortest distance between the first pad portion and the second pad portion.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a field plate, a gate electrode, and a first dielectric layer. The substrate has a top surface. The substrate includes a first drift region with a first conductivity type extending from the top surface of the substrate into the substrate, and includes a second drill region with the first conductivity type extending from the top surface of the substrate into the substrate and adjacent to the first drift region. The field plate is over the substrate. The gate electrode has a first portion and a second portion, wherein the first portion of the gate electrode is located over the field plate. The first dielectric layer is between the substrate and the field plate. The first portion of the gate electrode is overlapping with a boundary of the first drift region and the second drift region in the substrate.

Abstract: A heat sealable polyester film and a method for manufacturing the same are provided. The heat sealable polyester film is made from a recycled polyester material. The heat sealable polyester film includes a base layer and a heat sealable layer formed on at least one surface of the base layer. The heat sealable layer is formed from a first polyester composition. A main component of the first polyester composition is regenerated polyethylene terephthalate and the first polyester composition further includes at least one of 1,4-butanediol, isophthalic acid, neopentyl glycol, and polybutylene terephthalate. A heat sealing temperature of the heat sealable polyester film ranges from 120° C. to 230° C.

Abstract: A low-heat-loss operation method of a line-focusing heat collection system and the line-focusing heat collection system are provided. The method includes the following steps. Solar energy is utilized to preheat a collector tube in an empty tube state, so that the collector tube is in a preheating mode. After a set preheating temperature is reached, a heat transfer working medium is injected into the collector tube. In the injection process of the heat transfer working medium, an injection section of the collector tube is converted into a focusing mode from a preheating mode. After heat collection is finished, the circulation of the heat transfer working medium is stopped, and the focusing mode of the collector tube is kept. In the drainage process of the heat transfer working medium, an emptying section of the collector tube is converted into a light heat-tracing mode from a focusing mode.

Abstract: This invention relates to the field of contaminated plastic waste decomposition. More specifically, the invention comprises methods and systems to decompose contaminated plastic waste and transform it into value-added products.

Abstract: A microfluidic detection unit comprises at least one fluid injection section, a fluid storage section and a detection section. Each fluid injection section defines a fluid outlet; the fluid storage section is in gas communication with the atmosphere and defines a fluid inlet; the detection section defines a first end in communication with the fluid outlet and a second end in communication with the fluid inlet. A height difference is defined between the fluid outlet and the fluid inlet along the direction of gravity. When a first fluid is injected from the at least one fluid injection section, the first fluid is driven by gravity to pass through the detection section and accumulate to form a droplet at the fluid inlet, such that a state of fluid pressure equilibrium of the first fluid is established.

Abstract: Low-level nodes (LLNs) that are communicatively connected to one another each have sensing capability and processing capability. High-level nodes (HLNs) that are communicatively connected to one another and to the LLNs each have processing capability more powerful than the processing capability of each LLN. The LLNs and the HLNs perform processing based on sensing events captured by the LLNs. The processing is performed by the LLNs and the HLNs to minimize data communication among the LLNs and the HLNs, and to provide for software-defined sensing.

Abstract: In some embodiments, the present disclosure relates to a method of forming an interconnect. The method includes forming an etch stop layer (ESL) over a lower conductive structure and forming one or more dielectric layers over the ESL. A first patterning process is performed on the one or more dielectric layers to form interconnect opening and a second patterning process is performed on the one or more dielectric layers to increase a depth of the interconnect opening and expose an upper surface of the ESL. A protective layer is selectively formed on sidewalls of the one or more dielectric layers forming the interconnect opening. A third patterning process is performed to remove portions of the ESL that are uncovered by the one or more dielectric layers and the protective layer and to expose the lower conductive structure. A conductive material is formed within the interconnect opening.

Abstract: A semiconductor package is provided, which includes a first chip disposed over a first package substrate, a molding compound surrounding the first chip, a first thermal interface material disposed over the first chip and the molding compound, a heat spreader disposed over the thermal interface material, and a second thermal interface material disposed over the heat spreader. The first thermal interface material and the second thermal interface material have an identical width.

Abstract: Some embodiments relate to an integrated chip including a plurality of conductive structures over a substrate. A first dielectric layer is disposed laterally between the conductive structures. A spacer structure is disposed between the first dielectric layer and the plurality of conductive structures. An etch stop layer overlies the plurality of conductive structures. The etch stop layer is disposed on upper surfaces of the spacer structure and the first dielectric layer.

Abstract: An antenna structure includes a first substrate and a second substrate. The first substrate includes: a semiconductor chip configured to transmit or receive a first radio-frequency (RF) signal; a first ground layer configured to provide ground to the semiconductor chip; and a signal layer arranged on a side of the first substrate opposite to the semiconductor chip and configured to transmit the first RF signal. The second substrate has an antenna array formed of antenna cells, each of the antenna cells including: a first antenna layer configured to radiate second RF signals based on the first RF signal; a second ground layer configured to provide ground to the first antenna layer. The antenna device further includes a plurality of connectors electrically coupling the semiconductor chip to the antenna array.

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first interconnect dielectric layer arranged over a substrate. An interconnect wire extends through the first interconnect dielectric layer, and a barrier structure is arranged directly over the interconnect wire. The integrated chip further includes an etch stop layer arranged over the barrier structure and surrounds outer sidewalls of the barrier structure. A second interconnect dielectric layer is arranged over the etch stop layer, and an interconnect via extends through the second interconnect dielectric layer, the etch stop layer, and the barrier structure to contact the interconnect wire.

Abstract: The disclosure discloses a heat-sealable polyester film, including a base layer and a heat-seal layer formed on the base layer. The heat-seal layer includes a physically regenerated polyester resin, a chemically regenerated polyester resin, and a modifier. The heat-sealable temperature of the heat-sealable polyester film is between 100° C. and 230° C.

Abstract: In a method of de-mounting a pellicle from a photo mask, the photo mask with the pellicle is placed on a pellicle holder. The pellicle is attached to the photo mask by a plurality of micro structures. The plurality of micro structures are detached from the photo mask by applying a force or energy to the plurality of micro structures before or without applying a pulling force to separate the pellicle from the photo mask. The pellicle is de-mounted from the photo mask. In one or more of the foregoing and following embodiments, the plurality of micro structures are made of an elastomer.

Abstract: An imaging optical lens assembly includes five lens elements, which are, in order from an object side to an image side along an optical path, a first lens element, a second lens element, a third lens element, a fourth lens element and a fifth lens element. Each of the five lens elements has an object-side surface towards the object side and an image-side surface towards the image side. The third lens element has positive refractive power. At least one of the object-side surface and the image-side surface of at least one of the five lens elements includes at least one critical point in an off-axis region thereof.

Abstract: An imaging optical lens assembly includes five lens elements. The five lens elements in order from an object side to an image side along an optical path are a first lens element, a second lens element, a third lens element, a fourth lens element and a fifth lens element. Each of the five lens elements has an object-side surface facing the object side and an image-side surface facing the image side. The first lens element has positive refractive power, the second lens element has negative refractive power and the third lens element has negative refractive power. With specific conditions being satisfied, the imaging optical lens assembly can be miniaturized while providing good image quality.

Abstract: In an embodiment, an interposer has a first side, a first integrated circuit device attached to the first side of the interposer with a first set of conductive connectors, each of the first set of conductive connectors having a first height, a first die package attached to the first side of the interposer with a second set of conductive connectors, the second set of conductive connectors including a first conductive connector and a second conductive connector, the first conductive connector having a second height, the second conductive connector having a third height, the third height being different than the second height, a first dummy conductive connector being between the first side of the interposer and the first die package, an underfill disposed beneath the first integrated circuit device and the first die package, and an encapsulant disposed around the first integrated circuit device and the first die package.