Abstract: Aspects of the invention include systems and methods configured to prevent masquerading service attacks. A non-limiting example computer-implemented method includes sending, from a first server in a cloud environment, a communication request comprising an application programming interface (API) key and a first server identifier to an identity and access management (IAM) server of the cloud environment. The API key can be uniquely assigned by the IAM server to a first component of the first server. The first server receives a credential that includes a token for the first component and sends the credential to a second server. The second server sends the credential, a second server identifier, and an identifier for a second component of the second server to the IAM server. The second server receives an acknowledgment from the IAM server and sends the acknowledgment to the first server.

Abstract: A substrate for a semiconductor package includes an array of bonding pads on a first surface of the substrate, and a plurality of raised structures adjacent to at least some of the bonding pads on the first surface of the substrate. The raised structures may be configured to control the height of solder balls contacting the array of bonding pads when the package substrate is mounted onto a support substrate. The raised structures may compensate for a deformation of the package substrate so that the co-planarity of the solder balls may be improved, thereby providing an improved solder connection between the package substrate and the support substrate.

Abstract: A driving circuit for driving an electronic element is provided. The drive circuit includes an inductive coupling circuit, a primary side circuit and a secondary side circuit. The inductive coupling circuit includes a primary winding and a secondary winding. The primary side circuit is electrically connected to an input voltage source, the primary winding and a first terminal of the electronic element. The secondary side circuit is electrically connected to the secondary winding, the primary side circuit and a second terminal of the electronic element. The driving circuit uses an electric energy stored in the primary side circuit and an electric energy stored in the secondary side circuit to drive the electronic element.

Abstract: A method of adaptably detecting dirt, occlusion and smudge on camera lens and image sensor includes capturing an image; subjecting original pixels of the image to sampling to result in sampled pixels; excluding outliers of the sampled pixels to result in retained pixels; obtaining an average value of the retained pixels; obtaining a tolerance value according to luminance values of the retained pixels; generating a threshold value for determining dirt, occlusion and smudge on camera lens and image sensor in the image according to the tolerance value and the average value of the retained pixels; and comparing a luminance value of at least one pixel of the image with a corresponding threshold value.

Abstract: A semiconductor device includes a gate structure, a first epitaxial layer, a second epitaxial layer and a cap layer. The gate structure is disposed on a substrate. The first epitaxial layer is disposed in the substrate and at two sides of the gate structure. The second epitaxial layer is disposed on the first epitaxial layer, in which an included angle between a surface of the second epitaxial layer and a horizontal direction is 15 degrees to 35 degrees. The cap layer is disposed on the second epitaxial layer.

Abstract: The invention provides a semiconductor cleaning step, which comprises the following steps: providing a chamber with a bottom surface and a sidewall, the chamber contains a heater on the bottom surface, performing a first deposition step to leave a residual layer on the sidewall of the chamber, performing a carbon deposition step to form a carbon layer on at least the surface of the heater, and performing a plasma cleaning step to simultaneously remove the residual layer on the sidewall of the chamber and the carbon layer on the bottom surface.

Abstract: A semiconductor package is provided, which includes a first chip disposed over a first package substrate, a molding compound surrounding the first chip, a first thermal interface material disposed over the first chip and the molding compound, a heat spreader disposed over the thermal interface material, and a second thermal interface material disposed over the heat spreader. The first thermal interface material and the second thermal interface material have an identical width.

Abstract: A semiconductor package includes: a die having a conductive pad at a first side of the die; and a redistribution structure over the first side of the die and electrically coupled to the die. The redistribution structure includes: a first dielectric layer including a first dielectric material; a first via in the first dielectric layer, where the first via is electrically coupled to the conductive pad of the die; and a first dielectric structure embedded in the first dielectric layer, where the first dielectric structure includes a second dielectric material different from the first dielectric material, where the first dielectric structure laterally surrounds the first via and contacts sidewalls of the first via.

Abstract: A method for fabricating a semiconductor device includes steps as follows. A gate structure is formed on a substrate. A fluorine-containing dopant is implanted into the substrate to form two lightly doped drain regions at two sides of the gate structure. A thermal treatment process is performed, in which a part of fluorine atoms of the fluorine-containing dopant diffuse onto a surface of the substrate. The part of fluorine atoms are removed.

Abstract: A semiconductor chiplet device includes a first die, a second die, a decoupling circuit and an interposer. The interposer includes a plurality of power traces and a plurality of ground traces. The first die and the second die are arranged on a first side of the interposer according to a configuration direction, and are coupled to the power traces and the ground traces. The decoupling circuit is arranged on a second side of the interposer, and is coupled to the power traces and the ground traces. The power traces and the ground traces are staggered with each other, and an extending direction of the ground traces and the power traces is the same as the configuration direction.

Abstract: Disclosed herein are methods for isolating antibody-producing cells that express antibody molecules specific for an interface between a target peptide and an MHC molecule. The methods disclosed herein utilize a blocking reagent when sorting cells such as splenocytes which permits enrichment of cells expressing rare antibody molecules that specifically recognize an MHC-peptide interface.

Abstract: The present invention uses the thinned second pad oxide layer as the pad oxide layer for the subsequent shallow trench isolation process. Therefore, it is not necessary to remove the entire pad oxide layer on the substrate surface after the P-type high-voltage ion well thermal drive-in process. The subsequent step of re-growing the pad oxide layer is omitted, thereby simplifying the process complexity.

Abstract: The present disclosure provides antibodies and antigen-binding fragments thereof that bind specifically to a coronavirus spike protein and methods of using such antibodies and fragments for treating or preventing viral infections (e.g., coronavirus infections).

Abstract: The present disclosure relates to a processing apparatus and a processing method, and the processing apparatus includes a chamber, a wafer carrier, at least one air inlet and at least one electrode, wherein the wafer carrier is extended into the chamber, the gas inlet is arranged around the chamber, and the electrode is disposed on the chamber.

Abstract: A method of inspecting flatness of substrate is provided and includes providing a substrate. N first inspecting points are selected from the surface of the substrate along a first straight line, where the coordinate of the i-th first inspecting point is (Xi,Yi,Zi). By using a formula “ D = ? i = 1 N - 1 ? ( X i + 1 - X i ) 2 + ( Y i + 1 - Y i ) 2 + ( Z i + 1 - Z i ) 2 ” , a first measurement length D is calculated. By using a formula “F=(D?S)/S”, a first flatness index F is calculated. S is the horizontal distance between 1st first inspecting point and N-th first inspecting point. When the first flatness index F is larger than a first threshold, the substrate is determined to be unqualified.

Abstract: A semiconductor structure includes a gate structure on a substrate and a spacer on the substrate and covering sidewalls of the gate structure. The gate structure includes an interfacial layer on the substrate, a high-k dielectric layer on the interfacial layer, and a metal portion on the high-k dielectric layer. The spacer covers sidewalls of the interfacial layer, the high-k dielectric layer, and the metal portion of the gate structure. A bottom width of a portion of the spacer on the sidewall of the interfacial layer is 1.1 times of a middle width of another portion of the spacer on the sidewall of the metal portion.

Abstract: Rendering digital twin include receiving metrics associated with a physical entity, the metrics received using an established real-time data synchronization protocol. The received metrics is analyzed. Based on the analysis of the received metrics, digital twin corresponding to the physical entity is updated, the digital twin being a virtual representation of the physical entity.

Abstract: Field effect transistor (FET) devices having a heterogeneous/segmented channel region and methods for fabricating the same are provided. In one example, a fin-like field effect transistor (FinFET) device includes a substrate, a fin structure disposed on the substrate, a segmented channel region formed in the fin structure, two source/drain (S/D) regions separated by the segmented channel region, and a gate structure wrapping around the segmented channel region. The segmented channel region further includes multiple channel segments sequentially arranged in the segmented channel region, and the multiple channel segments include a first channel segment and a second channel segment. The first channel segment includes a first channel barrier material dispersed therein and has a first energy barrier, and the first energy barrier is at least 0.1 electron volts (eV) in a carrier flow path between the two S/D regions when the FinFET device is not activated for operation.

Abstract: An approach for protecting container image and runtime data from host access may be presented. Container systems have allowed for more efficient utilization of computing resources, removing the requirement of a hypervisor, and packaging all necessary dependencies within an application. Preventing host access to container image and runtime data can be advantageous for a multitude of reasons. The approach herein may include, flattening a plurality of root file system of a one or more container images into a single layer. The approach may also include generating a container base image for each of the one or more flattened root file system. The approach may include encrypting each of the generated container base images with the flattened root file system.

Abstract: The application provides gene therapies for treating monogenic forms of nephrotic syndrome.