Abstract: A reticle thermal expansion calibration method includes exposing a group of wafers and generating a sub-recipe, performing data mining and data parsing to generate a plurality of overlay parameters, extracting a plurality of predetermined parameters from the plurality of overlay parameters, performing a linear regression on each of the predetermined parameters, and generating a coefficient of determination for each of the predetermined parameters.

Abstract: A resistive memory device includes a stacked structure and a copper via conductor structure. The stacked structure includes a first electrode, a second electrode, and a variable resistance layer. The second electrode is disposed above the first electrode in a vertical direction, and the variable resistance layer is disposed between the first electrode and the second electrode in the vertical direction. The copper via conductor structure is disposed under the stacked structure. The first electrode includes a tantalum nitride layer directly connected with the copper via conductor structure.

Abstract: The invention provides a target material structure suitable for semiconductor manufacturing process, which comprises an alloy made of a first metal and a second metal, the target material structure comprises an upper section and a lower section, the atomic ratio of the first metal to the second metal in the lower section is different from the atomic ratio of the first metal to the second metal in the upper section.

Abstract: A resistive random access memory includes a first dielectric layer, a bottom electrode on the first dielectric layer, a variable-resistance layer on the bottom electrode and having a U-shaped cross-sectional profile, a top electrode on the variable-resistance layer and filling a recess in the variable-resistance layer, a second dielectric layer on the first dielectric layer and around the variable-resistance layer and the bottom electrode, and a spacer on the bottom electrode and inserting between the variable-resistance layer and the second dielectric layer.

Abstract: A method for fabricating a semiconductor structure is disclosed. A substrate having a dielectric layer thereon and a gate trench formed in the dielectric layer is prepared. The substrate is subjected to a physical vapor deposition (PVD) process in a physical vapor deposition chamber equipped with an auto capacitance tuner to conformally deposit a metal layer on a top surface of the dielectric layer and on an interior surface of the gate trench. The PVD process comprises: (i) tuning the auto capacitance tuner to provide positive radio frequency (RF) bias to the substrate in the PVD chamber for a first time period; and (ii) subsequently tuning the auto capacitance tuner to provide negative RF bias to the substrate in the PVD chamber for a second time period.

Abstract: A low power mode control module for a crystal oscillator which performs the following steps: detecting whether an oscillation output signal of the crystal oscillator is output stably; when the oscillation output signal of the crystal oscillator is output stably, comparing at least one of an oscillation input signal and the oscillation output signal with an amplitude control signal to determine whether to adjust the amplitude control signal; when the amplitude control signal does not need to be adjusted, generating an upper bound reference voltage and a lower bound reference voltage associated with the amplitude control signal; and according to whether the oscillation output signal exceeds a reference voltage range of the upper reference voltage and the lower reference voltage, generating a low power mode control output signal associated with a crystal oscillator enable signal for enabling the crystal oscillator.

Abstract: A lithography film stack applied to an immersion lithography process includes a photoresist, a wavelength adjusting layer and a top coating layer. The photoresist is disposed on a substrate. The wavelength adjusting layer is disposed on the photoresist. The top coating layer is disposed on the wavelength adjusting layer. A refractive index of the wavelength adjusting layer is greater than a refractive index of the top coating layer and a refractive index of an immersion fluid of the immersion lithography process.

Abstract: A method of fabricating a semiconductor device includes providing a first fin extending from a substrate. In some embodiments, the method further includes forming a first gate stack over the first fin. In various examples, the method further includes forming a first doped layer along a surface of the first fin including beneath the first gate stack. In some cases, a first dopant species of the first doped layer is of a same polarity as a second dopant species of a source/drain feature of the semiconductor device.

Abstract: Computational systems and methods for predicting amino acid position(s) within a target peptide presented in a complex with a major histocompatibility complex (MHC) molecule (MHC-target peptide complex), the amino acid position(s) being involved in interacting with an antigen-recognition molecule that recognizes said MHC-target peptide complex, are presented herein. Computational systems and methods for estimating a number of off-target peptide(s) for an antigen-recognition molecule that recognizes a target peptide presented in a complex with a major histocompatibility complex (MHC) molecule (MHC-target peptide complex) is presented herein. Computational systems and methods for ranking potential target peptides to mitigate off-target toxicity are presented herein. Such computational systems and methods can streamline development of effective, well tolerated antigen-recognition molecules to treat diseases.

Abstract: An apparatus for thermally processing a substrate includes a substrate support for holding the substrate and lamps disposed above the substrate support. The lamps are grouped into concentric lamp zones including a center zone comprised of a center lamp and peripheral lamps surrounding the center lamp. A center sleeve is coupled to the center lamp and peripheral sleeves are coupled to the peripheral lamps, respectively, for directing radiated heat to the substrate during thermal processing. The center sleeve has a higher surface roughness than that of the peripheral sleeves.

Abstract: A method for forming a semiconductor structure includes forming a gate structure on a substrate, performing a deposition process to form a nitride layer to cover the substrate and the gate structure, performing an in-situ annealing process to the nitride layer, and performing an anisotropic etching process to the nitride layer after the in-situ annealing process to form a spacer on a sidewall of the gate structure.

Abstract: A method for fabricating a semiconductor device is disclosed. A substrate having thereon at least one metal-oxide-semiconductor (MOS) transistor is provided. A stress memorization technique (SMT) process is performed. The SMT process includes steps of depositing an SMT film covering the at least one MOS transistor on the substrate, and subjecting the SMT film to a thermal process. A lithographic process and an etching process are performed to form a patterned SMT film. A silicide layer is formed on the MOS transistor. The patterned SMT film acts as a salicide block layer when forming the silicide layer.

Abstract: The invention provides a resistive random access memory (RRAM) structure, which comprises a lower electrode located on a substrate, a resistance switching layer located on the lower electrode, and an upper electrode located on the resistance switching layer, the resistive random access memory structure has a flat top surface and two inclined sidewalls as viewed from a sectional view, and the maximum width of the resistance switching layer is greater than the maximum width of the upper electrode.

Abstract: Disclosed is a gripping mechanism including a first bracket, a second bracket, a first guide rod, a third bracket, an actuating module, a gripping block and two grippers. The second bracket is connected to the first bracket. The third bracket is connected to the second bracket. The actuating module is disposed on the third bracket. The gripping block is slidably disposed on the third bracket and is connected to the actuating module. The two grippers are fixed on the terminal end of the third bracket distal from the first bracket and the second bracket, wherein the gripping block is located between the actuating module and the two grippers and the actuating module is adapted to drive the gripping block to slide close to or slide away from the two grippers. A mobile robot is also disclosed.

Abstract: Disclosed is a gripping mechanism including a first bracket, a second bracket, a first guide rod, a third bracket, an actuating module, a gripping block and a gripper. The second bracket is pivotally connected to the first bracket. The first guide rod is fixed on the second bracket. The third bracket is slidably connected to the first guide rod. The actuating module is disposed on the third bracket. The gripping block is slidably disposed on the third bracket, wherein the gripping block is connected to the actuating module. The gripper is fixed on the third bracket, wherein the actuating module is located between the first guide rod and the gripping block, and the gripping block is located between the actuating module and the gripper. A mobile robot is also disclosed.

Abstract: An embodiment semiconductor package includes a package substrate, a first semiconductor die electrically and mechanically coupled to the package substrate, a second semiconductor die electrically and mechanically coupled to the package substrate, a non-conductive film formed between the first semiconductor die and the package substrate, and a capillary underfill material formed between the second semiconductor die and the package substrate. The non-conductive film may be formed in a first region over a surface of the package substrate and the capillary underfill material may be formed over a second region of the surface of the package substrate, such that the second region surrounds the first region in a plan view. The semiconductor package may further include a multi-die frame partially surrounding the first semiconductor die and the second semiconductor die such that a multi-die chip is formed that includes the first semiconductor die, the second semiconductor die, and the multi-die frame.

Abstract: The invention provides a semiconductor cleaning step, which comprises the following steps: providing a chamber with a bottom surface and a sidewall, the chamber contains a heater on the bottom surface, performing a first deposition step to leave a residual layer on the sidewall of the chamber, performing a carbon deposition step to form a carbon layer on at least the surface of the heater, and performing a plasma cleaning step to simultaneously remove the residual layer on the sidewall of the chamber and the carbon layer on the bottom surface.

Abstract: An energy storage device capable of suppressing battery spread of battery fire includes a control module and a plurality of battery modules, and the battery modules respectively include an accommodation space, a plurality of battery packs, a plurality of temperature sensors and a controller. The controller provides a first control signal to notify the control module based on an ambient temperature detected by one of the temperature sensors being greater than or equal to a first specific temperature range. The control module is used to transfer a battery capacity of an abnormal battery module of the battery modules providing the first control signal to a backup energy storage module, and the backup energy storage module includes the battery modules except the abnormal battery module or a next-stage device.