Abstract: An IC socket includes a socket body with a plurality of contacts disposed therein, a cover rotatablely coupled to the socket body and at least one slider in the socket body. The socket body defines a receiving space for receiving an IC package, and the cover has a driving member. The slider has one end engageable with the driving member and the other end extending toward the receiving space. When the IC socket is in a close position, the slider touches the IC package or close to the IC package to keep a reliable connection between the IC socket and the IC package.

Abstract: A virtual ground nitride read-only memory array has a matrix of nitride read-only memory cells in which during an erase operation the non-erasing side of nitride read-only memory cells are connected to a common node for enhancing the erase uniformity of the nitride read-only memory array. If an operation requests erasing on the left side of nitride read-only memory cells, a positive voltage is supplied from an internal power supply to the left side for each of the nitride read-only memory cells, and the right side for each of the nitride read-only memory cells is discharged to a common node. The voltage level of the common mode is selected to be sufficiently high in order to prevent from punch through while at the same time sufficiently low to maintain the lateral electric field for erase operation to function optimally.

Abstract: A method for fabricating semiconductor device is provided. A high stress layer formed on, under or on both sides of the transistors of the semiconductor device is employed as a cap layer. A specific region is then defined through photo resistor mask, and the stress of the region is changed by ion implanting. Therefore, compressive stress and tensile stress occur on the high stress layer. According the disclosed method, the high stress layer may simultaneously improve the characteristics of the transistors formed on the same wafer. Further, the mobility of the carriers of the device is enhanced.

Abstract: A program verification method for a memory device having a virtual array including a plurality of memory cells determines if leakage current passes through one or more neighboring memory cells to the programmed memory cell. The programmed memory cell is verified based on a first threshold state if leakage current is determined to pass through one or more neighboring memory cells. The programmed memory cell is verified based on a second threshold state if the leakage current is not determined to pass through one or more neighboring memory cells.

Abstract: A pressure device for a test socket includes a main pressure body (70) defining a substantially rectangular opening sized to allow a sub-pressure body (60) to be therewithin, and the sub-pressure body accommodated within the main pressure body. At least one passage (601, 701) is formed on lateral sections between the main pressure body and the sub-pressure body. A fastening member (10) is to be within the at least one passage for fastening the sub-pressure body to the main pressure body, and includes a core section (101) and an end (102) attached to the core section. The end of the fastening member defines a surface shaped to facilitate a wrench to be engaged therewithin, which is easy to extract the fastening member from the passages of the main pressure body and the sub-pressure body by the use of the conventional wrench available in the factory.

Abstract: A virtual ground NROM array has a matrix of NROM cells in which during an erase operation the non-erasing side of NROM cells are connected to a common node for enhancing the erase uniformity of the NROM array. If an operation requests erasing on the left side of NROM cells, a positive voltage is supplied from an internal power supply to the left side for each of the NROM cells, and the right side for each of the NROM cells is discharged to a common node. If an operation requests erasing the right side of NROM cells, a positive voltage is supplied from the internal power supply to the right side for each of the NROM cells, and the right side for each of the NROM cells is connected to the common node. The voltage level of the common mode is selected to be sufficiently high in order to prevent from punch through while at the same time sufficiently low to maintain the lateral electric field for erase operation to function optimally.

Abstract: A program verification method for a memory device having a virtual array including a plurality of memory cells determines if leakage current passes through one or more neighboring memory cells to the programmed memory cell. The programmed memory cell is verified based on a first threshold state if leakage current is determined to pass through one or more neighboring memory cells. The programmed memory cell is verified based on a second threshold state if the leakage current is not determined to pass through one or more neighboring memory cells.

Abstract: A memory device is disclosed that includes a plurality of word lines and a plurality of memory cells operating in one of a plurality of modes and coupled to at least one of the word lines. The memory device also includes a plurality of reference lines and reference cells. Each reference cell corresponds to one of the operating modes, supplies a reference current for the corresponding mode, and is coupled to at least one of the reference lines. A reference cell current from a reference cell can also be compared to a target range and, if outside the target range, the voltage level on a corresponding referece line can be adjusted accordingly such that the reference current falls within the target range (i.e., reference current trimming).

Abstract: A NROM memory device includes an array of memory cells and first and second bit lines. The first and second bit lines are coupled to opposite sides of the memory cells. During an erase operation, one of the sides of the memory cells receives a positive voltage and the other side couples to a common node or a limited current source. Methods are also disclosed that can easily screen for marginal memory cells based on a threshold voltage distribution of the memory cells.

Abstract: A method for fabricating semiconductor device is provided. A high stress layer formed on, under or on both sides of the transistors of the semiconductor device is employed as a cap layer. A specific region is then defined through photo resistor mask, and the stress of the region is changed by ion implanting. Therefore, compressive stress and tensile stress occur on the high stress layer. According the disclosed method, the high stress layer may simultaneously improve the characteristics of the transistors formed on the same wafer. Further, the mobility of the carriers of the device is enhanced.

Abstract: A method for fabricating semiconductor device is provided. A high stress layer formed on, under or on both sides of the transistors of the semiconductor device is employed as a cap layer. A specific region is then defined through photo resistor mask, and the stress of the region is changed by ion implanting. Therefore, compressive stress and tensile stress occur on the high stress layer. According the disclosed method, the high stress layer may simultaneously improve the characteristics of the transistors formed on the same wafer. Further, the mobility of the carriers of the device is enhanced.

Abstract: A method for fabricating semiconductor device is provided. A high stress layer formed on, under or on both sides of the transistors of the semiconductor device is employed as a cap layer. A specific region is then defined through photo resistor mask, and the stress of the region is changed by ion implanting. Therefore, compressive stress and tensile stress occur on the high stress layer. According the disclosed method, the high stress layer may simultaneously improve the characteristics of the transistors formed on the same wafer. Further, the mobility of the carriers of the device is enhanced.

Abstract: A current produced by a current mirror in a clock generator circuit for a charge pump is controlled by a temperature dependent, current-adjusting MOSFET which has a threshold voltage (Vt) that varies with temperature. As the temperature varies, the current through the a temperature dependent, current-adjusting MOSFET varies, to thereby control a frequency of the clock generator circuit. The MOSFET can be provided with a temperature-independent power supply, so that the current of the temperature dependent, current-adjusting MOSFET can be more closely controlled.

Abstract: A current produced by a current mirror in a clock generator circuit for a charge pump is controlled by a temperature dependent, current-adjusting MOSFET which has a threshold voltage (Vt) that varies with temperature. As the temperature varies, the current through the a temperature dependent, current-adjusting MOSFET varies, to thereby control a frequency of the clock generator circuit. The MOSFET can be provided with a temperature-independent power supply, so that the current of the temperature dependent, current-adjusting MOSFET can be more closely controlled.

Abstract: A heating injection apparatus for vapor liquid delivery system includes inert gas purging part and thermostat device. Inert gas purging parts includes a liquid injector, a three-way valve, an exhausting branch and a purging gas. The three-way valve is used to connect purging gas, injector and exhausting branch. Liquid source resides in front of the liquid injector, and be injected into a gas line by liquid injector, besides the purging gas is used to purging out the liquid source remains on liquid injector to prevent polymerization. The temperature setting of thermostat device can be adjusted to meet liquid source requirement, and used to heating gas to demand production temperature before the gas enters the CVD system, and the thermostat device heats gas more efficiently, quickly and keep the gas temperature constant.

Abstract: The present invention provides a method for forming low dielectric constant layer in a semiconductor device comprising providing the semiconductor device. A dielectric layer is formed on the semiconductor device, which has a constituent of a plurality of unsaturated carbon bonds compounds. The dielectric layer is then treated with hydrogen. The purpose of treatment of hydrogen is to form saturated carbon bonds compounds for unexhausted unsaturated carbon bonds in the dielectric layer.

Abstract: A semiconductor wafer is provided, which has a low k layer positioned on the semiconductor wafer and a dual damascene structure positioned in the low k layer. The dual damascene structure includes a trench and a via hole, the via hole connecting to a conductive layer laid beneath. A barrier layer is formed at a temperature of 300 to 400° C. to cover the dual damascene structure and the low k layer. Thereafter, the semiconductor wafer is cooled to room temperature.

Abstract: A method of fabricating a DRAM capacitor uses tungsten nitride in the process of forming a capacitor. The structure of the capacitor is simple and the process is easily executed. Furthermore, the invention provides a method of forming tungsten nitride, comprising a step of implanting nitrogen into a tungsten silicide layer and a step of executing a rapid thermal process under ammonia gas to form a tungsten nitride layer on the surface of the tungsten silicide layer. The method of fabricating a DRAM capacitor comprises forming the tungsten silicide layer after forming a part smaller than a bottom electrode of the capacitor from doped polysilicon and forming tungsten nitride on the surface of the tungsten nitride layer.

Abstract: A method is directed to forming a barrier layer, particularly suitable for use in a copper fabrication process. A substrate is provided. A conductive structure layer may have already been formed on the substrate. An inter-metal dielectric layer is formed over the substrate. The inter-metal dielectric layer is then patterned to form an opening that exposes the substrate. An oxygen getter layer is formed over the inter-metal dielectric layer and the opening. A barrier layer is formed on the oxygen getterlayer. A copper layer is deposited over the barrier layer. An oxidation of the oxygen getter layer is occurred in the subsequent high temperature steps. An oxide layer, serving as another barrier layer, is formed thereon. The oxygen getter layer includes any metal which can easily react with oxygen, such as titanium or tantalum.

Abstract: The present invention provides a method for forming low dielectric constant layer in a semiconductor device comprising providing the semiconductor device. A dielectric layer is formed on the semiconductor device, which has a constituent of a plurality of unsaturated carbon bonds compounds. The dielectric layer is then treated with hydrogen. The purpose of treatment of hydrogen is to form saturated carbon bonds compounds for unexhausted unsaturated carbon bonds in the dielectric layer.