Abstract: A method for manufacturing dual damascene structure is disclosed. A dielectric layer is formed over a substrate having a conductive region. A dual damascene process is carried out to form a trench and a via openings exposing the conductive region in the openings. Sequentially a first barrier metal layer, a second barrier metal layer comprised of tungsten material, and a seed layer are formed over the dielectric layer and covering the sidewalls and the bottom of the trench and the via openings. A conductive metal layer is then blanket deposited over the dielectric layer and the top surface is planarized to remove portions of the conductive metal layer, the seed layer, the second barrier metal layer, and the first barrier metal layer until the dielectric layer is exposed.

Abstract: A method for forming metal interconnects. A substrate having a metal line is provided. A dielectric layer with an opening exposing the metal line is formed over the substrate, which dielectric layer further comprises an etching stop layer. After forming a covering layer conformal to a profile of the opening over the substrate, a portion of the covering layer in a bottom of the opening is removed to expose the metal line. A conformal barrier layer and a metal layer are formed sequentially in the opening and the metal layer fills up the opening. After forming a cap layer covering the substrate, the cap layer and the dielectric layer are defined to form a second opening. Next, remove the dielectric layer exposed by the opening, thus forming air-gaps.

Abstract: A method of fabricating a DRAM capacitor uses tungsten nitride in the process of forming a capacitor. The structure of the capacitor is simple and the process is easily executed. Furthermore, the invention provides a method of forming tungsten nitride, comprising a step of implanting nitrogen into a tungsten silicide layer and a step of executing a rapid thermal process under ammonia gas to form a tungsten nitride layer on the surface of the tungsten silicide layer. The method of fabricating a DRAM capacitor comprises forming the tungsten silicide layer after forming a part smaller than a bottom electrode of the capacitor from doped polysilicon and forming tungsten nitride on the surface of the tungsten nitride layer.

Abstract: A method for manufacturing the lower electrode of a DRAM capacitor. The method includes depositing polysilicon instead of amorphous silicon to form the lower electrode. Because polysilicon has a higher depositing temperature, it has a higher depositing rate capable of shortening depositing time. After forming the polysilicon lower electrode, the upper portion of the polysilicon layer is transformed into an amorphous layer by bombarding the polysilicon layer with ions to damage its internal structure. Eventually, hemispherical grain silicon is able to grow over the lower electrode, thereby increasing its surface area.

Abstract: A method that enhances performance of copper damascene by embedding TiN layer is proposed. The spirit of the invention is that a CVD TiN layer is inserted between the copper seed layer and the dielectric layer to improve the quality of copper layer. Herein, the TiN layer can either be located between the copper seed layer and the barrier layer or be located between the barrier layer and the dielectric layer. Because the barrier layer and the copper seed layer are formed by physical vapor deposition in current mass product, a higher side wall converge of the CVD TiN layer can be obtained owing to the higher conformity nature of CVD technology. Therefore, a better sidewall CVD TiN converge serves as an extra protection layer for copper self diffusion. Furthermore, it also acts as a copper seed layer to remedy side wall void problems due to copper seed layer discontinuity. Thus, not only the quality of copper layer is improved but also the performance of copper damascene process is enhanced.

Abstract: A method of making a semiconductor device including a MOS transistor provides an insulator formed on a semiconductor substrate and a gate electrode formed on the insulator. Source/drain regions are formed within the substrate on either side of the gate electrode. A layer of titanium is sputtered onto the semiconductor device, and a layer of titanium nitride is direct sputtered over the titanium layer using a titanium nitride target. The device is annealed at a first temperature to form a structure including titanium silicide on the polysilicon electrode, titanium silicide on the surface of the source/drain regions, unreacted titanium over the silicide regions, and titanium nitride over the unreacted metal. The unreacted titanium and titanium nitride are removed from the structure, and the structure is annealed at a higher temperature than the first temperature to form a lower resistivity titanium silicide.

Abstract: A method of fabricating a copper capping layer. A silicon rich nitride layer is formed on an exposed copper layer. Since the silicon rich nitride layer has more dangling bonds inside, the silicon in the silicon rich nitride layer easily reacts with the copper and a copper silicide layer is formed between the copper and the silicon rich nitride layer. Therefore, adhesion of the copper and the silicon rich nitride layer can be improved.

Abstract: The proposed invention is used to prevent the bridging issue of salicide process and also to provide a self-aligned contacted process in conventional self-aligned silicide process.

Abstract: A self-aligned silicide process. A substrate has at least a transistor formed thereon. A thin metal layer is formed over the substrate. A first rapid thermal process is performed to make the metal layer react with polysilicon of the gate and of the source/drain regions to form a first metal silicide layer. The metal layer, which does not react with polysilicon, is removed. A selective raised salicide process is performed to form a second metal silicide layer on the first metal silicide layer. A second rapid thermal process is performed to transform the first metal silicide layer and the second metal silicide layer from a high-resistance C49 phase into a low-resistance C54 phase.

Abstract: A method for forming an inter-metal dielectric layer without voids therein is described. Wiring lines are formed on a provided substrate. Each of the wiring lines comprises a protective layer thereon. A liner layer is formed over the substrate and over the wiring lines. An FSG layer is formed on the liner layer by using HDPCVD. A thickness of the FSG layer is about 0.9-1 times a thickness of the wiring lines. A cap layer is formed on the FSG layer using HDPCVD. A thickness of the cap layer is about 0.2-0.3 times a thickness of the wiring lines. An oxide layer is formed on the cap layer to achieve a predetermined thickness. A part of the dielectric layer is removed to obtain a planarized surface.

Abstract: A method for forming a gate. A gate oxide layer, a polysilicon layer and a barrier layer are subsequently formed on a substrate, on which an isolation structure is formed. A conductive layer is formed on the barrier layer by sputtering deposition using titanium silicide with a low silicon content as a target. A rapid thermal process (RTP) is performed to remove the polymer nodule formed by sputtering deposition. An anti-reflection layer is formed on the conductive layer. The anti-reflection layer, the conductive layer and the barrier layer are patterned by the etchant composed of chlorine/nitrogen/hexafluoroethane until the polysilicon layer is exposed. Using the anti-reflection layer, the conductive layer and the barrier layer as a mask, the exposed polysilicon layer and the gate oxide layer underlying the exposed polysilicon layer are removed by the etchant composed of chlorine/hydrogen bromide/helium/oxygen until the substrate is exposed and a gate is formed.

Abstract: A method of making a semiconductor device including a MOS transistor provides an insulator formed on a semiconductor substrate and a gate electrode formed on the insulator. Source/drain regions are formed within the substrate on either side of the gate electrode. A layer of titanium is sputtered onto the semiconductor device, and a layer of titanium nitride is direct sputtered over the titanium layer using a titanium nitride target. The device is annealed at a first temperature to form a structure including titanium silicide on the polysilicon electrode, titanium silicide on the surface of the source/drain regions, unreacted titanium over the silicide regions, and titanium nitride over the unreacted metal The unreacted titanium and titanium nitride are removed from the structure, and the structure is annealed at a higher temperature than the first temperature to form a lower resistivity titanium silicide.

Abstract: A fabrication method for a salicide gate is described, wherein the method comprising forming a gate structure on a substrate. The gate structure comprises a polysilicon gate and a selective-deposition dummy layer formed on the polysilicon gate. Source/drain regions are then formed on both sides of the gate structure in the substrate. After this, a dielectric layer is selectively deposited on the substrate, wherein the dielectric layer on the source/drain regions is thicker than the dielectric layer on the anti-reflection layer. A portion of the dielectric layer is removed until the anti-reflection layer is exposed. The anti-reflection layer is subsequently removed, followed by forming a salicide layer on the polysilicon gate to complete the manufacturing of a salicide gate.

Abstract: The proposed invention is a salicide process that is used to avoid bridge phenomena.

Abstract: This invention provides a method of forming a self-aligned silicide of a semiconductor wafer, the surface of the semiconductor wafer comprising at least one silicon device. A cobalt-containing metallic layer is formed on the semiconductor wafer which covers on the surface of the silicon device. A first thermal treatment process is performed to rapidly heat the semiconductor wafer up to 300˜500° C. for 10˜50 seconds and form Co2Si on the surface of the silicon device. A second thermal treatment process is performed to rapidly heat the semiconductor wafer up to 400˜680° C. for 20˜50 seconds and then cool down the semiconductor wafer afterwards so as to convert Co2Si into CoSi. An etching process is performed to remove the metallic layer. A third thermal treatment process is performed to rapidly heat the semiconductor wafer up to 700˜950° C. for 30˜60 seconds and then cool down the semiconductor wafer afterward so as to convert CoSi into the self-aligned silicide.

Abstract: A method of testing a leakage current caused by a self-aligned silicide process is described. The invention uses different test structure to monitor degree of and reason for a leakage current caused by a self-aligned silicide process. While monitoring a self-aligned silicide process performed on a metal-oxide semiconductor transistor without a LDD region, in addition to considering a leakage current occurring from the metal silicide layer to the junction and occurring at edge of the metal silicide layer, the invention further considers a leakage current at comer of the metal silicide layer. For a metal-oxide semiconductor transistor having a LDD region, the invention further considers a leakage current from the metal silicide layer to the LDD region. The invention monitors a leakage current at comer of the metal silicide layer.

Abstract: A method of forming bonding pad commences by forming a conformal barrier layer on a provided inter-metal dielectric layer. A first metal layer is formed on the barrier layer to partially fill the trench. A thin glue layer is formed on the first metal layer. A second metal layer is formed on the glue layer to fill the trench. The second metal layer, the glue layer, the first metal layer and the barrier layer are partially removed to expose the dielectric layer. A bonding pad structure is thus formed in the trench. The bonding pad structure comprises a first metal pad and a second metal pad.

Abstract: A process of forming a silicide on a source/drain region of a MOS device is described, wherein the MOS device has a gate spacer partially covering the source/drain region. A silicon film is formed on the source/drain region, wherein the silicon film has a portion near the gate spacer substantially thinner than the other portion of the silicon film. The silicon film is reacted with a metal film to wholly consume the portion of the silicon film near the gate spacer and to partially consume the other portion of the silicon film.

Abstract: A method of fabricating an HSG electrode. An electrode is defined before the formation of an HSG layer. The HSG layer is then formed on the top surface and the side wall of the electrode. The HSG layer is thermal oxidized in a furnace by rapid thermal process, and a silicon oxide layer is formed on the surface of the HSG layer. Dipping the electrode into a dilute solution of hydrogen fluoride or buffered oxide etching (BOE), the silicon oxide layer is lifted off while an HSG structure is remained on the top surface and the side wall of the electrode.

Abstract: A method for forming an inter-metal dielectric layer without voids therein is described. Wiring lines are formed on a provided substrate. Each of the wiring lines comprises a protective layer thereon. A liner layer is formed over the substrate and over the wiring lines. A fluorinated silicate glass (FSG) layer is formed on the liner layer by using high density plasma chemical vapor deposition (HDPCVD). A thickness of the FSG layer is about 0.9-1 times a thickness of the wiring lines. A cap layer is formed on the FSG layer using HDPCVD. A thickness of the cap layer is about 0.2-0.3 times a thickness of the wiring lines. An oxide layer is formed on the cap layer to achieve a predetermined thickness. A part of the dielectric layer is removed to obtain a planarized surface.