Patents by Inventor Wen-Yi Tan

Wen-Yi Tan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250133790
    Abstract: A semiconductor device includes a gate structure, a first epitaxial layer, a second epitaxial layer and a cap layer. The gate structure is disposed on a substrate. The first epitaxial layer is disposed in the substrate and at two sides of the gate structure. The second epitaxial layer is disposed on the first epitaxial layer, in which an included angle between a surface of the second epitaxial layer and a horizontal direction is 15 degrees to 35 degrees. The cap layer is disposed on the second epitaxial layer.
    Type: Application
    Filed: December 25, 2023
    Publication date: April 24, 2025
    Applicant: United Semiconductor (Xiamen) Co., Ltd.
    Inventors: Yong XIE, Shih-Hsien HUANG, Sheng-Hsu LIU, Qiang GAO, Wen Yi TAN
  • Patent number: 12276020
    Abstract: The invention provides a semiconductor cleaning step, which comprises the following steps: providing a chamber with a bottom surface and a sidewall, the chamber contains a heater on the bottom surface, performing a first deposition step to leave a residual layer on the sidewall of the chamber, performing a carbon deposition step to form a carbon layer on at least the surface of the heater, and performing a plasma cleaning step to simultaneously remove the residual layer on the sidewall of the chamber and the carbon layer on the bottom surface.
    Type: Grant
    Filed: July 10, 2023
    Date of Patent: April 15, 2025
    Assignee: United Semiconductor (Xiamen) Co., Ltd.
    Inventors: William Zheng, Shih-Feng Su, Chih-Chien Huang, Wen Yi Tan, Ji He Huang
  • Publication number: 20250118560
    Abstract: A method for fabricating a semiconductor device includes steps as follows. A gate structure is formed on a substrate. A fluorine-containing dopant is implanted into the substrate to form two lightly doped drain regions at two sides of the gate structure. A thermal treatment process is performed, in which a part of fluorine atoms of the fluorine-containing dopant diffuse onto a surface of the substrate. The part of fluorine atoms are removed.
    Type: Application
    Filed: November 16, 2023
    Publication date: April 10, 2025
    Applicant: United Semiconductor (Xiamen) Co., Ltd.
    Inventors: LINSHAN YUAN, Guang Yang, Liangfeng Zhang, Jinjian OUYANG, Chin-Chun Huang, WEN YI TAN
  • Publication number: 20250095994
    Abstract: The present invention uses the thinned second pad oxide layer as the pad oxide layer for the subsequent shallow trench isolation process. Therefore, it is not necessary to remove the entire pad oxide layer on the substrate surface after the P-type high-voltage ion well thermal drive-in process. The subsequent step of re-growing the pad oxide layer is omitted, thereby simplifying the process complexity.
    Type: Application
    Filed: October 13, 2023
    Publication date: March 20, 2025
    Applicant: United Semiconductor (Xiamen) Co., Ltd.
    Inventors: Jian Liu, CHEN CHEN, Chin-Chun Huang, WEN YI TAN, JINJIAN OUYANG
  • Publication number: 20250087466
    Abstract: The present disclosure relates to a processing apparatus and a processing method, and the processing apparatus includes a chamber, a wafer carrier, at least one air inlet and at least one electrode, wherein the wafer carrier is extended into the chamber, the gas inlet is arranged around the chamber, and the electrode is disposed on the chamber.
    Type: Application
    Filed: October 19, 2023
    Publication date: March 13, 2025
    Applicant: United Semiconductor (Xiamen) Co., Ltd.
    Inventors: Ching-Shu Lo, Yan Cai, Tsung Che Lin, Wen Yi Tan
  • Publication number: 20250081498
    Abstract: A semiconductor structure includes a gate structure on a substrate and a spacer on the substrate and covering sidewalls of the gate structure. The gate structure includes an interfacial layer on the substrate, a high-k dielectric layer on the interfacial layer, and a metal portion on the high-k dielectric layer. The spacer covers sidewalls of the interfacial layer, the high-k dielectric layer, and the metal portion of the gate structure. A bottom width of a portion of the spacer on the sidewall of the interfacial layer is 1.1 times of a middle width of another portion of the spacer on the sidewall of the metal portion.
    Type: Application
    Filed: November 18, 2024
    Publication date: March 6, 2025
    Applicant: United Semiconductor (Xiamen) Co., Ltd.
    Inventors: Jun Wu, Shih-Hsien Huang, Wen Yi Tan, Feng Gao
  • Publication number: 20250072077
    Abstract: A semiconductor device and method of fabricating the same, the semiconductor device includes a substrate, a metal gate structure, at least one dummy body, two source/drain regions, and a dielectric layer. The metal gate structure is disposed on the substrate. The at least one dummy body is disposed within the metal gate structure. The source/drain regions are disposed at two sides of the metal gate structure respectively in the substrate. The dielectric layer is disposed on the substrate, around the metal gate structure.
    Type: Application
    Filed: September 19, 2023
    Publication date: February 27, 2025
    Applicant: United Semiconductor (Xiamen) Co., Ltd.
    Inventors: Wei-Chun Chang, You-Di Jhang, Han-Min Huang, Chin-Chun Huang, WEN YI TAN
  • Publication number: 20250062132
    Abstract: The invention provides an etching method of a semiconductor structure, which comprises providing a substrate with a gate structure, an oxide layer and a first nitride layer beside the gate structure, and performing an etching step to remove the first nitride layer and keep the oxide layer, wherein in the etching step, the etching selectivity ratio of the etched nitride material to the etched oxide material is greater than 300.
    Type: Application
    Filed: September 14, 2023
    Publication date: February 20, 2025
    Applicant: United Semiconductor (Xiamen) Co., Ltd.
    Inventors: Yanjie Liu, Bing Du, LaiJiao Liu, Hailong Gu, Chin-Chun Huang, Wen Yi Tan
  • Publication number: 20250063802
    Abstract: A method for fabricating a semiconductor device includes the steps of first providing a substrate having a first transistor region and a second transistor region and then forming a first gate structure on the first transistor region and a second gate structure on the second transistor region, in which the first gate structure includes a first hard mask, the second gate structure includes a second hard mask, and the first hard mask and the second hard mask have different thicknesses. Next, a patterned mask is formed around the first gate structure and the second gate structure, and then part of the first hard mask is removed.
    Type: Application
    Filed: September 13, 2023
    Publication date: February 20, 2025
    Applicant: United Semiconductor (Xiamen) Co., Ltd.
    Inventors: Wen Wei Wang, Xiang Xiang Zhou, Xiang Wang, Hailong Gu, Wen Yi Tan
  • Patent number: 12219886
    Abstract: A resistive memory device includes a stacked structure and a copper via conductor structure. The stacked structure includes a first electrode, a second electrode, and a variable resistance layer. The second electrode is disposed above the first electrode in a vertical direction, and the variable resistance layer is disposed between the first electrode and the second electrode in the vertical direction. The copper via conductor structure is disposed under the stacked structure. The first electrode includes a tantalum nitride layer directly connected with the copper via conductor structure.
    Type: Grant
    Filed: July 29, 2021
    Date of Patent: February 4, 2025
    Assignee: United Semiconductor (Xiamen) Co., Ltd.
    Inventors: Shuzhi Zou, Dejin Kong, Xiang Bo Kong, Chin-Chun Huang, Wen Yi Tan
  • Patent number: 12216072
    Abstract: A reticle thermal expansion calibration method includes exposing a group of wafers and generating a sub-recipe, performing data mining and data parsing to generate a plurality of overlay parameters, extracting a plurality of predetermined parameters from the plurality of overlay parameters, performing a linear regression on each of the predetermined parameters, and generating a coefficient of determination for each of the predetermined parameters.
    Type: Grant
    Filed: August 22, 2021
    Date of Patent: February 4, 2025
    Assignee: United Semiconductor (Xiamen) Co., Ltd.
    Inventors: Maohua Ren, Yuan-Chi Pai, Wen Yi Tan
  • Publication number: 20250034696
    Abstract: The invention provides a target material structure suitable for semiconductor manufacturing process, which comprises an alloy made of a first metal and a second metal, the target material structure comprises an upper section and a lower section, the atomic ratio of the first metal to the second metal in the lower section is different from the atomic ratio of the first metal to the second metal in the upper section.
    Type: Application
    Filed: August 21, 2023
    Publication date: January 30, 2025
    Applicant: United Semiconductor (Xiamen) Co., Ltd.
    Inventors: Yongbo Xu, Shouguo Zhang, Wen Yi Tan, Ching-Shu Lo
  • Patent number: 12213391
    Abstract: A resistive random access memory includes a first dielectric layer, a bottom electrode on the first dielectric layer, a variable-resistance layer on the bottom electrode and having a U-shaped cross-sectional profile, a top electrode on the variable-resistance layer and filling a recess in the variable-resistance layer, a second dielectric layer on the first dielectric layer and around the variable-resistance layer and the bottom electrode, and a spacer on the bottom electrode and inserting between the variable-resistance layer and the second dielectric layer.
    Type: Grant
    Filed: July 5, 2023
    Date of Patent: January 28, 2025
    Assignee: United Semiconductor (Xiamen) Co., Ltd.
    Inventors: Dejin Kong, Jinjian Ouyang, Xiang Bo Kong, Wen Yi Tan
  • Publication number: 20250031433
    Abstract: A method for fabricating a semiconductor structure is disclosed. A substrate having a dielectric layer thereon and a gate trench formed in the dielectric layer is prepared. The substrate is subjected to a physical vapor deposition (PVD) process in a physical vapor deposition chamber equipped with an auto capacitance tuner to conformally deposit a metal layer on a top surface of the dielectric layer and on an interior surface of the gate trench. The PVD process comprises: (i) tuning the auto capacitance tuner to provide positive radio frequency (RF) bias to the substrate in the PVD chamber for a first time period; and (ii) subsequently tuning the auto capacitance tuner to provide negative RF bias to the substrate in the PVD chamber for a second time period.
    Type: Application
    Filed: August 14, 2023
    Publication date: January 23, 2025
    Applicant: United Semiconductor (Xiamen) Co., Ltd.
    Inventors: Shouguo Zhang, Yongbo Xu, Wen Yi Tan
  • Patent number: 12204247
    Abstract: A lithography film stack applied to an immersion lithography process includes a photoresist, a wavelength adjusting layer and a top coating layer. The photoresist is disposed on a substrate. The wavelength adjusting layer is disposed on the photoresist. The top coating layer is disposed on the wavelength adjusting layer. A refractive index of the wavelength adjusting layer is greater than a refractive index of the top coating layer and a refractive index of an immersion fluid of the immersion lithography process.
    Type: Grant
    Filed: February 9, 2023
    Date of Patent: January 21, 2025
    Assignee: United Semiconductor (Xiamen) Co., Ltd.
    Inventors: Ching-Shu Lo, Yuan-Chi Pai, Maohua Ren, Wen Yi Tan
  • Patent number: 12191171
    Abstract: An apparatus for thermally processing a substrate includes a substrate support for holding the substrate and lamps disposed above the substrate support. The lamps are grouped into concentric lamp zones including a center zone comprised of a center lamp and peripheral lamps surrounding the center lamp. A center sleeve is coupled to the center lamp and peripheral sleeves are coupled to the peripheral lamps, respectively, for directing radiated heat to the substrate during thermal processing. The center sleeve has a higher surface roughness than that of the peripheral sleeves.
    Type: Grant
    Filed: December 19, 2021
    Date of Patent: January 7, 2025
    Assignee: United Semiconductor (Xiamen) Co., Ltd.
    Inventors: Xin Zhi He, Wen Yi Tan
  • Patent number: 12191211
    Abstract: A method for fabricating a semiconductor device is disclosed. A substrate having thereon at least one metal-oxide-semiconductor (MOS) transistor is provided. A stress memorization technique (SMT) process is performed. The SMT process includes steps of depositing an SMT film covering the at least one MOS transistor on the substrate, and subjecting the SMT film to a thermal process. A lithographic process and an etching process are performed to form a patterned SMT film. A silicide layer is formed on the MOS transistor. The patterned SMT film acts as a salicide block layer when forming the silicide layer.
    Type: Grant
    Filed: May 25, 2022
    Date of Patent: January 7, 2025
    Assignee: United Semiconductor (Xiamen) Co., Ltd.
    Inventors: Linshan Yuan, Guang Yang, Yuchun Guo, Jinjian Ouyang, Chin-Chun Huang, Wen Yi Tan
  • Patent number: 12191377
    Abstract: A method for forming a semiconductor structure includes forming a gate structure on a substrate, performing a deposition process to form a nitride layer to cover the substrate and the gate structure, performing an in-situ annealing process to the nitride layer, and performing an anisotropic etching process to the nitride layer after the in-situ annealing process to form a spacer on a sidewall of the gate structure.
    Type: Grant
    Filed: December 22, 2021
    Date of Patent: January 7, 2025
    Assignee: United Semiconductor (Xiamen) Co., Ltd.
    Inventors: Jun Wu, Shih-Hsien Huang, Wen Yi Tan, Feng Gao
  • Publication number: 20250008850
    Abstract: The invention provides a resistive random access memory (RRAM) structure, which comprises a lower electrode located on a substrate, a resistance switching layer located on the lower electrode, and an upper electrode located on the resistance switching layer, the resistive random access memory structure has a flat top surface and two inclined sidewalls as viewed from a sectional view, and the maximum width of the resistance switching layer is greater than the maximum width of the upper electrode.
    Type: Application
    Filed: August 10, 2023
    Publication date: January 2, 2025
    Applicant: United Semiconductor (Xiamen) Co., Ltd.
    Inventors: WEIKUN LIN, Wen Yi Tan
  • Publication number: 20240401191
    Abstract: The invention provides a semiconductor cleaning step, which comprises the following steps: providing a chamber with a bottom surface and a sidewall, the chamber contains a heater on the bottom surface, performing a first deposition step to leave a residual layer on the sidewall of the chamber, performing a carbon deposition step to form a carbon layer on at least the surface of the heater, and performing a plasma cleaning step to simultaneously remove the residual layer on the sidewall of the chamber and the carbon layer on the bottom surface.
    Type: Application
    Filed: July 10, 2023
    Publication date: December 5, 2024
    Applicant: United Semiconductor (Xiamen) Co., Ltd.
    Inventors: William Zheng, Shih-Feng Su, Chih-Chien Huang, WEN YI TAN, Ji He Huang