Abstract: An integrated circuit includes: a substrate having a resistive random-access memory area and a resistor area; a first dielectric layer and a second dielectric layer sequentially disposed on the substrate; a patterned stacked structure having a bottom conductive layer, an insulating layer and a top conductive layer stacked from bottom to top sandwiched by the first dielectric layer and the second dielectric layer; a first metal plug and a second metal plug disposed in the second dielectric layer and contacting the top conductive layer and the bottom conductive layer of the resistive random-access memory area respectively, thereby constituting a resistive random-access memory cell; and, a third metal plug and a fourth metal plug disposed in the second dielectric layer and contacting the bottom conductive layer or the top conductive layer of the resistor area, thereby constituting a resistor cell. A method of forming said integrated circuit is also provided.

Abstract: An integrated circuit includes: a substrate having a resistive random-access memory area and a resistor area; a first dielectric layer and a second dielectric layer sequentially disposed on the substrate; a patterned stacked structure having a bottom conductive layer, an insulating layer and a top conductive layer stacked from bottom to top sandwiched by the first dielectric layer and the second dielectric layer; a first metal plug and a second metal plug disposed in the second dielectric layer and contacting the top conductive layer and the bottom conductive layer of the resistive random-access memory area respectively, thereby constituting a resistive random-access memory cell; and, a third metal plug and a fourth metal plug disposed in the second dielectric layer and contacting the bottom conductive layer or the top conductive layer of the resistor area, thereby constituting a resistor cell. A method of forming said integrated circuit is also provided.

Abstract: A transistor structure includes a substrate. A gate structure is disposed on the substrate. A hexagonal-shaped trench is disposed in the substrate at one side of the gate structure. A first epitaxial layer including first-type dopants is disposed in the hexagonal-shaped trench and contacts the hexagonal-shaped trench. A second epitaxial layer including second-type dopants is disposed in the hexagon-shaped trench. The first epitaxial layer is outside of the second epitaxial layer. The second epitaxial layer serves as a source/drain doped region of the transistor structure. The first-type dopants and the second-type dopants are of different conductive types.

Abstract: A method for forming a gate structure used in borderless contact etching is disclosed including the steps described below. Forming a conductive layer on a substrate, followed by forming a first silicon nitride layer on the conductive layer. The next step is to pattern a gate electrode by etching all the layers formed in the steps mentioned previously. The following steps is to form a second silicon nitride layer on the surface of the gate electrode and the substrate. Finally, etching the second silicon nitride layer to form a nitride spacer on the side walls of the gate electrode. The altitude of the nitride spacer is higher than the altitude of the first silicon nitride layer.