Abstract: A semiconductor transistor structure includes a substrate with a first conductivity type, a fin structure grown on the substrate, and a gate on the fin structure. The fin structure includes a first epitaxial layer having a second conductivity type opposite to the first conductivity type, a second epitaxial layer on the first epitaxial layer, and a third epitaxial layer having the second conductivity type on the second epitaxial layer.

Abstract: A manufacturing method of a contact structure includes the following steps. A substrate is provided, and the substrate includes a first region and a second region. A dielectric layer is formed on the substrate. A photoresist layer is formed on the dielectric layer. An exposure process is performed. The exposure process includes first exposure steps and second exposure steps. Each of the first exposure steps is performed to a part of the first region of the substrate. Each of the second exposure steps is performed to a part of the second region of the substrate. Each of the second exposure steps is performed with a first overlay shift by a first predetermined distance. A develop process is performed for forming openings in the photoresist layer.

Abstract: The invention provides an improved semiconductor deposition method, which comprises providing a deposition machine, the deposition machine includes a chamber connected with a pipeline, putting a first wafer into the chamber, and performing a pipeline cleaning step, the pipeline cleaning step includes: cutting off the path between the pipeline and the chamber by turning off a plurality of valve switches, and introducing a gas from the pipeline to move along a first path of the pipeline. Then, a deposition step is performed on the first wafer to deposit a first material layer on the surface of the first wafer, the deposition step includes opening a plurality of valve switches to communicate the path between the pipeline and the chamber, and introducing the gas into the chamber along a second path of the pipeline.

Abstract: The invention provides a safety system for a cleanroom, which comprises a cleanroom garment provided with a plurality of RFID (radio frequency identification) tags, a face recognition device arranged at an entrance of the cleanroom, and a first RFID reader arranged beside at least one machine in the cleanroom, wherein the first RFID reader is used for identifying the RFID tags on the cleanroom garment, and a KVM network power interrupter connected to a display screen of the machine.

Abstract: A resistive random access memory includes a bottom electrode, a variable-resistance layer on the bottom electrode and having a U-shaped cross-sectional profile, and a top electrode on the variable-resistance layer and filling a recess in the variable-resistance layer.

Abstract: A method for aligning to a pattern on a wafer is disclosed. The method includes the steps of obtaining a first inline image from a first sample wafer, obtaining a first contour pattern of an alignment mark pattern from the first inline image, using the first contour pattern to generate a first synthetic image in black and white pixels, using the first synthetic image as a reference to recognize the alignment mark pattern on a tested wafer, and aligning to a tested pattern on the tested wafer according to a position of the alignment mark pattern on the tested wafer and a coordinate information.

Abstract: The invention provides a semiconductor testkey pattern, the semiconductor testkey pattern includes a high density device region and a plurality of resistor pairs surrounding the high density device region, wherein each resistor pair includes two mutually symmetrical resistor patterns.

Abstract: A dispatch management method for Pilot-run on a computer and applicable to chemical mechanical polishing machines includes: generating initialization work schedules; filtering the initialization work schedules according to respective adaptability parameters to generate intermediate work schedules; performing crossing operations on the intermediate work schedules to generate M sets of crossed work schedules; performing mutation calculations on contents of the intermediate work schedules and the M sets of crossed work schedules to generate mutated work schedules; performing optimization calculations on the intermediate work schedules, the crossed work schedules and the mutated work schedules to generate a target work schedule; and automatically performing dispatch on the CMP machines according to the target work schedule.

Abstract: A method of decreasing height differences of STIs includes providing a substrate comprising a peripheral circuit region. The peripheral circuit region includes a P-type transistor region and an N-type transistor region. A first STI and a third STI are respectively disposed within the N-type transistor region and the P-type transistor region. Later, a first mask is formed to cover the N-type transistor region. Then, an N-type well is formed in the P-type transistor region and part of the third STI is removed by taking the first mask as a mask. Next, the first mask is removed. After that, a second mask is formed to cover the P-type transistor region. Subsequently, a P-type well is formed in the N-type transistor region and part of the first STI is removed by taking the second mask as a mask. Finally, the second mask is removed.

Abstract: A radiofrequency device includes a semiconductor substrate, an inductor structure, a shielding structure, and a mask pattern. The semiconductor substrate includes a first region and a second region. The inductor structure is disposed on the first region of the semiconductor substrate. The shielding structure is disposed on the first region of the semiconductor substrate and located between the inductor structure and the semiconductor substrate in a vertical direction. The mask pattern is disposed on the semiconductor substrate. A first portion of the mask pattern is disposed on the shielding structure and directly contacts the shielding structure, and a top surface of the shielding structure is completely covered by the first portion of the mask pattern.

Abstract: A method for fabricating a semiconductor transistor is disclosed. A substrate of a first conductivity type is provided. An ion well of a second conductivity type is formed in the substrate. An epitaxial channel layer of the first conductivity type is grown from the main surface of the substrate. A gate dielectric layer is formed on the epitaxial channel layer. A gate is formed on the gate dielectric layer. A source region and a drain region are then formed in the substrate. The source region and the drain region have the first conductivity type.

Abstract: The invention provides a method for adjusting the resistance value of a thin film resistor layer in a semiconductor structure, which comprises forming the thin film resistor layer, the material of the thin film resistor layer comprises titanium nitride, and the thin film resistor layer has an original resistance value, a mask layer with tensile force is formed above the thin film resistor layer, and the mask layer with tensile force changes a lattice size of the thin film resistor layer, so that the lattice size of the thin film resistor layer becomes larger and the original resistance value of the thin film resistor layer is reduced.

Abstract: A method of decreasing height differences of STIs includes providing a substrate comprising a peripheral circuit region. The peripheral circuit region includes a P-type transistor region and an N-type transistor region. A first STI and a third STI are respectively disposed within the N-type transistor region and the P-type transistor region. Later, a first mask is formed to cover the N-type transistor region. Then, an N-type well is formed in the P-type transistor region and part of the third STI is removed by taking the first mask as a mask. Next, the first mask is removed. After that, a second mask is formed to cover the P-type transistor region. Subsequently, a P-type well is formed in the N-type transistor region and part of the first STI is removed by taking the second mask as a mask. Finally, the second mask is removed.

Abstract: A manufacturing method of a contact structure includes the following steps. A substrate is provided, and the substrate includes a first region and a second region. A dielectric layer is formed on the substrate. A photoresist layer is formed on the dielectric layer. An exposure process is performed. The exposure process includes first exposure steps and second exposure steps. Each of the first exposure steps is performed to a part of the first region of the substrate. Each of the second exposure steps is performed to a part of the second region of the substrate. Each of the second exposure steps is performed with a first overlay shift by a first predetermined distance. A develop process is performed for forming openings in the photoresist layer.

Abstract: A resistive memory device includes a first electrode, a second electrode, a first metal oxide layer, a second metal oxide layer, and a multilayer insulator structure. The first metal oxide layer is disposed between the first electrode and the second electrode in a vertical direction. The second metal oxide layer is disposed between the first metal oxide layer and the second electrode in the vertical direction. The multilayer insulator structure is disposed between the first metal oxide layer and the second metal oxide layer in the vertical direction. The first metal oxide layer includes first metal atoms, the second metal oxide layer includes second metal atoms, and the multilayer insulator structure includes third metal atoms. Each of the third metal atoms is identical to each of the second metal atoms, and an atomic percent of the third metal atoms in the multilayer insulator structure gradually changes in the vertical direction.

Abstract: A semiconductor transistor is formed on a substrate of a first conductivity type. The substrate has a main surface. An ion well of the second conductivity type is disposed in the substrate. A source region and a drain region spaced apart from the source region are disposed within the ion well. The source region and the drain region have the first conductivity type. An epitaxial channel layer of the first conductivity type is grown from the main surface of the substrate and is disposed between the source region and the drain region. A gate is disposed on the epitaxial channel layer. A gate dielectric layer is disposed between gate and the epitaxial channel layer.

Abstract: A resistive memory device includes a first electrode, a second electrode, a first metal oxide layer, a second metal oxide layer, and a multilayer insulator structure. The first metal oxide layer is disposed between the first electrode and the second electrode in a vertical direction. The second metal oxide layer is disposed between the first metal oxide layer and the second electrode in the vertical direction. The multilayer insulator structure is disposed between the first metal oxide layer and the second metal oxide layer in the vertical direction. The first metal oxide layer includes first metal atoms, the second metal oxide layer includes second metal atoms, and the multilayer insulator structure includes third metal atoms. Each of the third metal atoms is identical to each of the second metal atoms, and an atomic percent of the third metal atoms in the multilayer insulator structure gradually changes in the vertical direction.

Abstract: A semiconductor device includes a patterned metal layer on a substrate, via conductors on the patterned metal layer, first inter-metal dielectric (IMD) patterns embedded in the patterned metal layer, and a second IMD pattern surrounding the patterned metal layer. Preferably, the first IMD patterns are between and without overlapping the via conductors in a top view.

Abstract: A method for forming a semiconductor device is disclosed. A semiconductor substrate having thereon an NMOS region, a PMOS region, and a non-silicide region is provided. An NMOS transistor is formed within the NMOS region and a PMOS transistor is formed within the PMOS region. A stress memorization technique (SMT) layer covering the NMOS region, the PMOS region, and the non-silicide region is formed. The SMT layer is removed from the PMOS region. A stress is transferred from the SMT layer into an N-channel of the NMOS transistor. The SMT layer is removed from the NMOS region, while leaving the SMT layer in the non-silicide region intact. A self-aligned silicidation (SAC) process is performed to form a salicide layer in the NMOS region and the PMOS region.

Abstract: An MIM capacitor includes a semiconductor substrate having a conductor layer thereon, a dielectric layer overlying the semiconductor substrate and the conductor layer, and a first capacitor electrode disposed on the dielectric layer. The first capacitor electrode partially overlaps with the conductor layer when viewed from above. A capacitor dielectric layer is disposed on the first capacitor electrode. A second capacitor electrode is disposed on the capacitor dielectric layer. At least one via is disposed in the dielectric layer and electrically connecting the first capacitor electrode with the conductor layer.