Abstract: A method for fabricating a semiconductor device includes steps as follows. A gate material layer is formed on a substrate, wherein the gate material layer includes an amorphous material having a phase transition temperature, and the amorphous material converts into a polycrystalline material at the phase transition temperature. A first hard mask is formed on the gate material layer at a first process temperature, wherein the first process temperature is less than the phase transition temperature. A second hard mask is formed on the first hard mask at a second process temperature, wherein the second process temperature is less than the phase transition temperature.

Abstract: The invention provides a semiconductor structure, which comprises a material layer, wherein a plurality of resistive random access memory cells are arranged on the material layer in an array, the array comprises a first outer ring, the first outer ring consists of some of the plurality of resistive random access memory cells and is located at the outermost ring of the array, and a peripheral metal layer, which at least connects a plurality of resistive random access memory cells located in the first outer ring in series into a loop.

Abstract: A reticle thermal expansion calibration method includes exposing a first group of wafers and generating a first sub-recipe, performing data mining and data parsing to generate a plurality of overlay parameters, performing a linear regression on each of the overlay parameters, and generating a first coefficient of determination for each of the overlay parameters.

Abstract: A machine learning intelligent dispatching system, including a history information module storing various history data, a basic information module storing various basic data, an algorithm module working out predicted runtimes and switching times of recipe groups based on the history data and basic data through machining learning, a robot module working out an optimized schedule result based on the history data and basic data and the predicted times, and a dispatching module dispatching lots according to the optimized schedule result to obtain an actual production result, and the actual production result is fed back to the robot module as a basis for the machine learning.

Abstract: A testkey structure for semiconductor device includes a substrate, a gate structure disposed on the substrate, and a plurality of first dummy gate structures disposed on the substrate and arranged around the gate structure. A bottom surface of the gate structure is lower than bottom surfaces of the first dummy gate structures. A top surface of the gate structure is flush with top surfaces of the first dummy gate structures.

Abstract: A semiconductor device includes a patterned metal layer on a substrate, via conductors on the patterned metal layer, first inter-metal dielectric (IMD) patterns embedded in the patterned metal layer, and a second IMD pattern surrounding the patterned metal layer. Preferably, the first IMD patterns are between and without overlapping the via conductors in a top view.

Abstract: The invention provides a method for manufacturing a semiconductor structure, which comprises the following steps: a high voltage metal oxide semiconductor (HVMOS) is provided, the high voltage metal oxide semiconductor comprises a substrate, and the substrate comprises an NMOS region and a PMOS region, the NMOS region and the PMOS region each comprise an oxide layer, a P-type ion doping step on the PMOS region is performed, the thickness of the oxide layer of the PMOS region is reduced during the P-type ion doping step, and an N-type ion doping step is then performed on the NMOS region after the P-type ion doping step, the thickness of the oxide layer of the NMOS region is reduced during the N-type ion doping step.

Abstract: A semiconductor device includes a resistor disposed on a second etching stop layer in the resistor forming region. A fourth interlayer dielectric layer covers the resistor and the second etch stop layer. A first via is located in the fourth interlayer dielectric layer and is electrically connected to a terminal of the resistor. By forming the resistor in BEOL process, the problem of the contact stop depth difference that affects the process window and causes the reduced yield can be improved.

Abstract: The invention provides a semiconductor processing machine, which comprises a plurality of chambers, at least one of the chamber is a load-lock chamber, and the load-lock chamber comprises a bottom surface and a top lid opposite to the bottom surface; and a gas pipeline is connected with the top lid of the load-lock chamber.

Abstract: A test key structure includes a substrate; a first metal pad disposed on the substrate; a second metal pad disposed in proximity to the first metal pad on the substrate; a gap between the first metal pad and the second metal pad; a first contact disposed on the first metal pad; and a second contact disposed on the second metal pad.

Abstract: A semiconductor transistor structure includes a substrate with a first conductivity type, a fin structure grown on the substrate, and a gate on the fin structure. The fin structure includes a first epitaxial layer having a second conductivity type opposite to the first conductivity type, a second epitaxial layer on the first epitaxial layer, and a third epitaxial layer having the second conductivity type on the second epitaxial layer.

Abstract: A method of removing a hard mask layer includes providing a gate. A hard mask layer covers and contacts a top surface of the gate. Two spacer structures respectively contacts two sides of the gate. Two first spacers are respectively disposed on the two spacer structures. Later, a wet etching process is performed to remove the hard mask layer and the first spacers and keep the spacer structures. An etchant is utilized in the wet etching process. A selective etching ratio of the silicon nitride to silicon oxide of the etchant is more than 90. The etchant includes Si(OH)4. A concentration of Si(OH)4. is greater than or equal to 3.95 ppm and smaller than or equal to 10 ppm.

Abstract: The invention provides an ion source structure of an ion implanter, which comprises an arc chamber, a filament in the arc chamber, and a cathode in the arc chamber, wherein the cathode has an upper surface and a lower surface, and at least one of the upper surface and the lower surface is non-planar.

Abstract: The present invention provides a semiconductor device and a method of fabricating the same, which includes a substrate, a gate structure, and a dielectric layer. The gate structure is disposed on the substrate and includes an inverted trapezoidal shape. The dielectric layer is disposed on the substrate, and the gate structure is disposed within the dielectric layer. The gate structure includes a metal gate structure or a polysilicon gate structure.

Abstract: A method for wafer image equalization includes obtaining a wafer image, converting the wafer image into bitmap data, generating a grayscale distribution of RGB pixels according to the bitmap data, generating a grayscale cumulative probability distribution of the RGB pixels according to the grayscale distribution, generating a mapping function according to the grayscale cumulative probability distribution of the RGB pixels, converting the grayscale distribution of the RGB pixels by the mapping function into an equalized grayscale distribution of the RGB pixels, and generating an equalized wafer image according to the equalized grayscale distribution of the RGB pixels.

Abstract: The invention provides a photoresist coating method, which comprises the following steps: providing a wafer with a pattern on the wafer, placing the wafer on a spinner, injecting a photoresist on a central region of the wafer from a nozzle, and carrying out a spin coating step, the spin coating step comprises: turning on the spinner to rotate the spinner to a first rotation speed, and raising the first rotation speed to a second rotation speed, and performing a plurality of brakes during the process of maintaining the second rotation speed, so that the second rotation speed instantly drops to a third rotation speed, and then rises to the second rotation speed again.

Abstract: A method of detecting wafer defects based on singularly valuable decomposition is provided in the present invention, including steps of input a wafer image, performing a preprocess to the wafer image through histogram equalization to obtain a preprocessed image, performing singularly valuable decomposition to the preprocessed image, performing defect magnification to the decomposed wafer image, reconstruct the magnified wafer image to obtain a defect saliency image, denoising the defect saliency image, and detecting defects in the denoised wafer image.

Abstract: A lithography film stack applied to an immersion lithography process includes a photoresist, a wavelength adjusting layer and a top coating layer. The photoresist is disposed on a substrate. The wavelength adjusting layer is disposed on the photoresist. The top coating layer is disposed on the wavelength adjusting layer. A refractive index of the wavelength adjusting layer is greater than a refractive index of the top coating layer and a refractive index of an immersion fluid of the immersion lithography process.

Abstract: A machine monitoring system includes a plurality of first machines and a control module. The first machines are for a first process. The control module is connected with the first machines. The control module is configured to: define each of the first machines as a high-risk first machine or a low-risk first machine according to a first risk score of each of the first machines; designate one of the first machines being defined as the high-risk first machine as a selected high-risk first machine; assign an object to be processed by the first process through the selected high-risk first machine to obtain a processed object; and determine whether to continue or stop to use the selected high-risk first machine according to a test result of the processed object.

Abstract: The invention provides an ion source structure of an ion implanter, which comprises an arc chamber, a filament in the arc chamber, and a cathode in the arc chamber, wherein the cathode has an upper surface and a lower surface, and at least one of the upper surface and the lower surface is non-planar.