Abstract: A deposition method for improving the step coverage of contact holes is disclosed. The method includes initially placing a semiconductor substrate on a chuck of a chamber, wherein the substrate has some contact holes. The chuck is firstly adjusted and conductive material is firstly deposited onto the substrate, wherein the direction of the first deposition is about vertical to the surface of the substrate, and therefore the bottom of the contact holes is then substantially deposited with the conductive material. Next, the chuck is secondly adjusted so that it has a tilt angle between the direction of the second deposition and rotation axis of the chuck. Finally, the chuck is continuously rotated and the conductive material is secondly deposited onto the substrate, and therefore the sidewall of the contact holes is then substantially deposited with the conductive material.

Abstract: A method for reducing multiple dominant pilots in a CDMA communication system comprises determining nulls of a first cell and pointing a sector antenna of a neighboring second cell towards one of said nulls of the first cell. A system is also described.

Abstract: A composition of Ba.sub.2 Ti.sub.9 O.sub.20 suitable for use in microwave wireless communications is provided. Ba.sub.2 Ti.sub.9 O.sub.20 doped with Zr is formed by combining starting materials containing barium, titanium and zirconium. In a preferred embodiment of the invention, zirconium-doped Ba.sub.2 Ti.sub.9 O.sub.20 is formed by combining BaCO.sub.3 and TiO.sub.2, and substituting an appropriate amount of ZrO.sub.2 for a portion of the TiO.sub.2. The relative proportion of Ba.sub.2 Ti.sub.9 O.sub.20 obtained as a result is increased over that which may be obtained using other dopants, such as tin (Sn). Forming Ba.sub.2 Ti.sub.9 O.sub.20 with a Zr dopant in the appropriate amount also results in greater stability of the dielectric constant, an increase in the quality factor, and a decrease in the temperature coefficient than exhibited by other compositions of Ba.sub.2 Ti.sub.9 O.sub.20 that lack a Zr dopant.

Abstract: A method of making a semiconductor device including a MOS transistor provides an insulator formed on a semiconductor substrate and a gate electrode formed on the insulator. Source/drain regions are formed within the substrate on either side of the gate electrode. A layer of titanium is sputtered onto the semiconductor device, and a layer of titanium nitride is direct sputtered over the titanium layer using a titanium nitride target. The device is annealed at a first temperature to form a structure including titanium silicide on the polysilicon electrode, titanium silicide on the surface of the source/drain regions, unreacted titanium over the silicide regions, and titanium nitride over the unreacted metal. The unreacted titanium and titanium nitride are removed from the structure, and the structure is annealed at a higher temperature than the first temperature to form a lower resistivity titanium silicide.

Abstract: The present invention provides a method of forming an undoped silicate glass layer on a semiconductor wafer by performing a high density plasma chemical vapor deposition process. The semiconductor wafer being positioned in a deposition chamber. The method comprises forming the undoped silicate glass layer by performing the high density plasma chemical vapor deposition process in the deposition chamber under the following conditions: an argon (Ar) flow rate of 40 to 70 sccm (standard cubic centimeter per minute); an oxygen (O.sub.2) flow rate of 90 to 120 sccm; a silane flow rate of 70 to 100 sccm; a gas pressure of 3 to 10 mtorr; a temperature of 300 to 400.degree. C.; and a low frequency power of 2500 to 3500 watts. Wherein the ratio of Ar to O.sub.2 is 0.53, and O.sub.2 to silane is 1.23.

Abstract: A unique method for solidification of solutions containing boric acid and/or borates is disclosed in this invention. The boron species in the solutions are polymerized to form polyborates, and the solutions are then solidified by mixing with solidification agents which are prepared completely from inorganic materials. Therefore, the solid form produced by this method has no aging problem. The boron species in the solution are not merely wastes to be encapsulated or embedded, they take part in the solidification reaction and share a major portion of total reactants. Thus, the total volume of solid forms produced in this invention is less than 1/10 of that produced in conventional cementation.

Abstract: A method for forming a high capacitance charge storage structure that can be applied to a substrate wafer having MOS transistor already formed thereon. The method is to form an insulating layer above the substrate wafer. Next, a contact window exposing a source/drain region is formed in the insulating layer. Then, a tungsten suicide layer, which functions as a lower electrode for the charge storage structure, is formed over the substrate. Thereafter, a tungsten nitride layer is formed over the tungsten silicide layer, and then a dielectric layer is formed over the tungsten nitride layer. The dielectric layer is preferably a tantalum oxide layer. Finally, a titanium nitride layer, which functions as an upper electrode for the charge storage structure, is formed over the tantalum oxide layer.

Abstract: A polysilicon layer is subsequently deposited on the dielectric layer by using CVD. Next, photolithography and etching process are used to etch the doped polysilicon layer, and form a bottom electrode of DRAM cell capacitor with U shape in cross section view. The next step of the formation is the deposition of a dielectric film along the surface of the bottom electrode of DRAM cell capacitor. Typically, the dielectric film is preferably formed of high dielectric film such as tantalum oxide (Ta.sub.2 0.sub.5). A conductive layer is deposited over the dielectric film. The conductive layer is used as the top storage node and is formed of titanium nitride(TiN). The methods of forming the top storage node, including sputtered-TiN, collimated-sputtering TiN, and CVD/MOCVD-TiN deposition. The purposes of sputtered-TiN and collimated-sputtering TiN processes can improve the poor step coverage of deep well of bottom electrode of DRAM cell capacitor and protect the Ta.sub.2 0.sub.

Abstract: An adaptive-selection method for memory access priority control in MPEG processor. The processor has functional modules that include an input interface, a CPU, an audio decoder, a video decoder, an audio processor, a video processor and a memory controller. Each of the modules gains control over the data bus via arbitration by the memory controller for accessing the memory. The access priority of the CPU to the data bus is maintained at a relatively lower level except when the CPU needs to perform parsing on the MPEG compressed data and implementing the initial decoding of the audio compressed data. The use of data bus bandwidth is therefore balanced among all the system resources thereby increasing the overall system performance.

Abstract: The present invention is a method for accurately estimating a location of a mobile-telephone using forward link power control. In one embodiment, the present invention comprises the steps of transmitting first, second and third signals from first, second and third base stations during first, second and third time intervals; decreasing the power level of the first base station during at least portions of the second and third time intervals; receiving a mobile-telephone signal having receive information indicating times-of-arrivals of the first, second and third signals at the mobile-telephone; and estimating a location of the mobile-telephone using the receive information and known locations of the first, second and third base stations. Advantageously, this embodiment of the present invention actually decreases the interference level contribution of the first base station, and requires little change to the network side of existing wireless communication standards and no change to the mobile-telephone side.

Abstract: A method for forming a gate structure used in borderless contact etching is disclosed including the steps described below. Forming a conductive layer on a substrate, followed by forming a first silicon nitride layer on the conductive layer. The next step is to pattern a gate electrode by etching all the layers formed in the steps mentioned previously. The following steps is to form a second silicon nitride layer on the surface of the gate electrode and the substrate. Finally, etching the second silicon nitride layer to form a nitride spacer on the side walls of the gate electrode. The altitude of the nitride spacer is higher than the altitude of the first silicon nitride layer.

Abstract: A micro needle probe apparatus that includes a probe and its associated electronic circuit. The electronic circuit is formed in a substrate and includes at least one metal interconnection layer. The probe is cantilevered over the electronic circuit and is composed of a metal probe arm, a support post that anchors one end of the probe arm to the substrate, and a micro needle mounted adjacent the moveable end of the probe arm. The probe apparatus may be used as the read/write mechanism of the moving-medium type memory device.

Abstract: The present invention relates to a method of manufacturing semiconductor components having a titanium nitride layer including the steps of providing a semiconductor substrate with a transistor including a gate and source/drain regions, depositing an insulating layer above the semiconductor substrate, etching the insulating layer to form an opening exposing the source/drain region below, depositing an ultra-thin titanium nitride layer having a grainy particulate profile and a thickness of about 0.5 nm to 2 nm around the edge and at the bottom of the opening, depositing a metallic layer over various aforementioned layers, and forming a metal silicide layer by heating the semiconductor substrate to allow the metallic layer to react with silicon on the semiconductor substrate surface.

Abstract: A memory device that comprises a planar memory medium and a probe device mounted opposite the planar memory medium. The probe device includes a substrate having a substrate surface and probe cells arrayed on the substrate surface. Each of the probe cells comprises a probe, an auxiliary electrode and a probe driving circuit. The probe is formed in the substrate, includes part of the substrate surface, and additionally includes a conductive needle projecting towards the memory medium. The conductive needle includes a needle tip adjacent the memory medium. The auxiliary electrode is mounted on the probe, and is located between the probe and the memory medium. The auxiliary electrode is disposed substantially parallel to, and spaced from, the substrate surface. The driving circuit is formed in the substrate and projects from the substrate surface towards the memory medium. The probe driving circuit has outputs electrically connected to the auxiliary electrode and the memory medium.

Abstract: A shower head assembly includes a housing including a first end portion engaged with a water outlet cap and a second end portion connected to a water source. The water outlet cap defines a plurality of outer nozzles arranged in a circular manner and a plurality of inner nozzles arranged in a circular manner. An adjusting device is mounted on a periphery of the housing for alternatively introducing water in the housing into the outer nozzles or the inner nozzles such that water can be sprayed outwardly via the outer nozzles or via the inner nozzles alternatively.

Abstract: Disclosed is a memory control device with partitioned memory control for use on a computer system configured based on a shared main memory architecture. The memory control device comprises a main memory controller connected with two sets of access control buses used respectively for partitioned control of the main memory. The main memory is partitioned into a main system dedicated memory segment and a shared resource memory segment respectively for use by the CPU and the peripheral system. A shared data path circuit is used to control data flow on the buses. When the CPU and the peripheral system both want to gain access to the main memory at the same time, the two sets of buses work independently to respectively connect the CPU to the main system dedicated memory segment and the peripheral system to the shared resource memory segment in the main memory for simultaneous, partitioned access to the main memory.

Abstract: A buffered probing device includes a cantilever-shaped probe having a micro-needle at its tip, and an electric circuit that applies electrical signals between the micro-needle and a probe target to which an electrical stimulus is applied. In one embodiment of the invention, the probe includes a suspension member having a spring constant per unit length that is less than that of a probe body. The micro-needle is formed on the suspension member. In another embodiment of the invention, the electric circuit applies oscillations at a specific frequency to the probe, such that the micro-needle is always or intermittently in contact with the surface of the probe target. As a result, wear of the needle is greatly reduced.

Abstract: A light modulator having the small volume and low power consumption of LCD displays together with the higher resolution and faster response time of CRT displays. The light modulator includes a substrate pair, an opaque light shielding layer, a shutter assembly composed of a shutter plate and a shutter suspension, and electrodes. The substrate pair includes a first substrate and a second substrate positioned parallel to each other and spaced from one another to define a cavity. The opaque light shielding layer is located on one of the substrates, and defines a translucent window. The shutter assembly is located in the cavity. The shutter plate is movably mounted adjacent the window by the shutter suspension. The shutter suspension includes elastic support members disposed between the shutter plate and the substrate pair.

Abstract: An apparatus for branch detecting a loop operation in a microprocessor. The apparatus includes a register, an ALU port, a predetector, an ALU, a flag generator and a branch detector. The register is provided for storing a loop information. Through the ALU port, the loop information is sent to the predetector and is predetected therein whenever the loop operation is about to proceed. A predetected result is then generated by the predetected and is sent to the branch detector to determine whether the loop operation has to be terminated. The ALU processes the loop information and updates new loop the register at the same time the predetection and detection tasks are performed by the predetector and the branch detector, respectively. The flag generator generates a flag which is independent of the detection and termination of the loop operation.