Abstract: A method includes forming a gate stack for a short-channel device and a longer-channel device; forming a first metal cap layer over the gate stacks for the short-channel device and the longer-channel device, wherein the first metal cap layer of the longer-channel device has a metal-cap recess; forming a first dielectric cap layer in the metal-cap recess; selectively removing in parallel, a portion of the gate stacks and first metal cap layer for the short-channel device and the longer-channel device; forming a first channel recess between spacers in the short-channel device and a second channel recess between a spacer and the first dielectric cap layer in the longer-channel device by the selectively removing; wherein each of the first channel recess and the second channel recess has a width dimension and a difference between the width dimensions of the first channel recess and second channel recess is less than 3 nm.

Abstract: Provided are structures and methods for forming structures with surfaces having a W-shaped profile. An exemplary method includes differentially etching a gate material to a recessed surface including a first and second horn and a valley located therebetween including first and second sections and a middle section therebetween; depositing an etch-retarding layer over the recessed surface including first and second edge regions and a central region therebetween, wherein the first edge region is located over the first horn and the first section, the second edge region is located over the second horn and the second section, the central region is located over the middle region, and the central region is thicker than the first edge region and the second edge region; and performing an etch process to recess the horns to establish the gate material with a W-shaped profile.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a dielectric layer over a substrate. The dielectric layer has a first trench over a first portion of the substrate and a second trench over a second portion of the substrate. The method includes forming a first work function layer in the first trench and the second trench. The method includes forming a first mask layer over the first work function layer in the first trench. The method includes removing the first work function layer exposed by the first mask layer. The method includes removing the first mask layer. The method includes forming a first gate electrode in the first trench and a second gate electrode in the second trench. The method includes forming a first hard mask layer in the first trench and a second hard mask layer in the second trench.

Abstract: A device comprising a package and a board. The package includes a substrate comprising a first surface and a second surface, a passive component coupled to the first surface of the substrate, an integrated device coupled to the second surface of the substrate, a back side metal layer coupled to a back side of the integrated device, a first solder interconnect coupled to the back side metal layer, and a plurality of solder interconnects coupled to the second surface of the substrate. The board is coupled to the package through the plurality of solder interconnects. The first solder interconnect is coupled to the board.

Abstract: Methods of cutting fins, and structures formed thereby, are described. In an embodiment, a structure includes a first fin and a second fin on a substrate, and a fin cut-fill structure disposed between the first fin and the second fin. The first fin and the second fin are longitudinally aligned. The fin cut-fill structure includes a liner on a first sidewall of the first fin, and an insulating fill material on a sidewall of the liner and on a second sidewall of the first fin. The liner is further on a surface of the first fin between the first sidewall of the first fin and the second sidewall of the first fin.

Abstract: A memory structure includes a pull-down transistor and a pull-up transistor stacked vertically in a Z-direction, a pass-gate transistor and a dummy transistor stacked vertically in the Z-direction, a dielectric structure, a connection structure, and a butt contact. The pull-down transistor and the pull-up transistor share a first gate structure. The pass-gate transistor and the dummy transistor share a second gate structure. The dielectric structure is between the first gate structure and the second gate structure in a Y-direction. The connection structure is over and electrically connected to the first gate structure and is over and electrically isolated from the second gate structure. The connection structure is an L-shape in a Y-Z cross-sectional view. The butt contact is directly over the connection structure and the second gate structure. The butt contact is electrically connected to the connection structure and a source/drain feature of the pass-gate transistor.

Abstract: A planetary bevel gear automatic limited slip differential includes five portions that are a main differential, a planetary bevel gear controller, a left drive axle shaft, a right drive axle shaft, and clutches. The planetary bevel gear controller includes an outer control unit and an inner control unit, the outer control unit includes four planetary bevel gears on an outer layer and a bevel gear fixed on a housing, and the inner control unit includes inner planetary bevel gears on an inner side and two bevel gears which have the same parameters and are meshed with the planetary bevel gears. The bevel gears are fixedly connected with outer rings of two overrunning clutches, respectively, and inner rings of the overrunning clutches and the right drive axle shaft are connected together by splines.

Abstract: A method and a system for identifying a glacial lake outburst debris flow (GLODF) are provided. The method is obtained based on considering induced influences of slopes of channels and particle sizes of source particles on the GLODF. The method not only compensates for deficiencies in identifying the GLODF, but also realizes determination of the GLODF, which provides data basis for disaster prevention and control layout such as monitoring and early warning on a glacial lake and assists preventing and managing disasters caused by the GLODF. Meanwhile, multiple parameters used in the method are easy and convenient to obtain, and the parameters can be directly used on site, which saves engineering cost, improves working efficiency, and has high practical and promotional value in environmental protection and disaster prevention and mitigation.

Abstract: A semiconductor device includes a substrate, a first gate, a plurality of second gates and a resistor. The substrate is defined with an active region and a resistor region. The first gate is disposed in the active region. The first gate has a first length extending along a first direction and a second length extending along a second direction. The plurality of second gates are disposed in the resistor region. Each of the second gates has a third length extending along the first direction and a fourth length extending along the second direction. The first length is equal to the third length, and the second length is equal to the fourth length. The resistor is disposed on the plurality of second gates.

Abstract: A flexible power plant based on supercritical carbon dioxide power circulation in combination with seawater desalination and a control method thereof are provided. By means of the integrated process based on supercritical carbon dioxide power circulation in combination with seawater desalination, the power plant uses a new two-stage supercritical CO2 Breton circulation to reduce the exhaust temperature of the heat source, enhance the thermal efficiency of the thermodynamic circulation, improve the flexibility and adjustability of the output of the thermal power plant, and correspondingly raise the utilization efficiency of the low-temperature dynamic heat source in the seawater desalination process, so that it serves as a standing “flexible load” of the power plant, and further enhance the overall efficiency and flexibility of the power plant.

Abstract: The present invention provides compounds useful as inhibitors of PDK1. The present invention also provides compositions thereof, and methods of treating PDK1-mediated diseases.

Abstract: The present disclosure provides a cemented filling material with bionic structure, a preparation method and an application thereof, and belongs to the field of structural modification methods of cemented filling materials and research and development of civil materials with ultra-high energy absorption characteristics. The cemented filling material with bionic structure includes a bionic honeycomb skeleton and cemented filling slurry, where the cemented filling slurry is poured in the bionic honeycomb skeleton.

Abstract: A die bonding tool having a tool head including a plurality of openings fluidly coupled to a vacuum source to selectively secure a semiconductor die onto the tool head via the application of a suction force. The plurality of openings have non-uniform cross-sectional areas, including one or more first openings having a first cross-sectional area and one or more second openings having a second cross-sectional area that is greater than the first cross-section area. A first minimum offset distance between each of the first openings and any peripheral edge of the tool head is less than a second minimum offset distance between each of the second openings and any peripheral edge of the tool head. The configuration of the openings in the tool head may improve bonding of the semiconductor die to a substrate by inhibiting air becoming trapped between the semiconductor die and the substrate during the bonding process.

Abstract: Embodiments of the present disclosure relate to a SRAM (static random access memory) bit cell. More particularly, embodiments of the present disclosure relate to a single port, 8T SRAM cell with write enhance pass gate transistors. Particularly, two write enhance pass gate transistors are parallelly connected with the pass gate transistors in a standard 6T SRAM cell. The write enhance pass gate transistors are independently controlled from the pass gate transistor using a write enhance word line. In some embodiments, the single port, 8T SRAM cell according to the present disclosure may be implemented by stacked complementary FETs. Empty or dummy PMOS transistors in a standard 6T stacked CFET SRAM cell are used as pass gate transistors or write enhance pass gate transistors.

Abstract: A fixing device includes a main body, a sliding block, and a fixing rod. The main body has a sliding rail and a guiding hole, and the sliding rail which is disposed at a front side of the main body vertically extends. The guiding hole adjoins the sliding rail and horizontally extends through the main body. The sliding block is slidably connected to the sliding rail. The fixing rod is movably connected to the sliding block extending through the guiding hole, and the sliding block is configured to move along the sliding rail and enable the guiding hole to drive the fixing rod to horizontally move.

Abstract: An immersion cooling system includes a tank, an isolation plate and a condenser. The tank includes a base plate and a sidewall connected with the base plate. The sidewall defines with the base plate a space configured to accommodate a cooling liquid. The isolation plate connects with the sidewall or the base plate and divides the space into a first subsidiary space and a second subsidiary space. The first subsidiary space is configured to accommodate electronic equipment which is immersed in the cooling liquid. The isolation plate and the base plate are separated from each other. The sidewall surrounds the condenser. A vertical projection of the condenser towards the base plate at least partially overlaps with the second subsidiary space. The electronic equipment evaporates a portion of the cooling liquid to form a vapor. The condenser is configured to condense the vapor into a liquid form.

Abstract: An immersion cooling system includes a pressure seal tank, an electronic apparatus, a pressure balance pipe and a relief valve. The pressure seal tank is configured to store coolant. A vapor space is formed in the pressure seal tank above the liquid level of the coolant. The electronic apparatus is completely immersed in the coolant. The pressure balance pipe has a gas collection length. The first port of the pressure balance pipe is disposed on the top surface of the pressure seal tank. The relief valve is disposed on the second port of the pressure balance pipe. The second port is farther away from the top surface of the pressure seal tank than the first port. The gas collection length of the pressure equalization tube allows the concentration of vaporized coolant at the first port to be greater than the concentration of vaporized coolant at the second port.

Abstract: An array substrate includes an opening area and a non-opening area, and further includes a first substrate, a gate insulating layer, a first interlayer insulating layer, and a second interlayer insulating layer. The gate insulating layer is disposed on the first substrate and located in the opening area and the non-opening area. The first interlayer insulating layer is disposed on a side of the gate insulating layer away from the first substrate and located in the non-opening area. The second interlayer insulating layer is disposed on a side of the first interlayer insulating layer away from the first substrate and located in the opening area and the non-opening area. A projection of the first interlayer insulating layer on the first substrate is tangent to or separated from a projection of the opening area on the first substrate. A display panel includes the array substrate.

Abstract: An image inference method is provided by the present disclosure. The method includes determining a target collocation scheme for an image according to an inference request and a preset weight table, the target collocation scheme including a hardware accelerator in an idle state and an estimated time duration of inferring the image. A usage state of the hardware accelerator in the target collocation scheme is updated to be an in use state, and the image is inferred according to the target collocation scheme. When the inferring of the image is completed, the usage state of the hardware accelerator is updated from the in use state to be the idle state. Once an actual time duration of inferring the image is obtained, the estimated time duration is updated to be the actual time duration.

Abstract: The present disclosure provides an immersion cooling system for a server cabinet including a plurality of server boxes, a cooling tank and a plurality of liquid connecting pipes. Each server box includes an electronic device immersed in the cooling liquid, and the electronic device generates a thermal energy so that part of the cooling liquid evaporates into a hot vapor. The cooling tank is connected to the plurality of server boxes and includes a condenser and a storage part. The condenser is connected to each server box and condenses the hot vapor to form the cooling liquid. The storage part storages the cooling liquid from the condenser. Two ends of the liquid connecting pipe is connected to the storage part and the server box respectively. The cooling liquid in the storage part and the cooling liquid of each server box are maintained in a same liquid level.