Abstract: A selection of a plurality of graphical user interface (GUI) components of a GUI is received. The selection is received so that the GUI can be tested. Attributes of the selection of GUI components are determined. Using the attributes, a default procedure for testing the GUI is determined. The default procedure includes a first set of input values for GUI components of the plurality of GUI components. The default procedure includes a first sequence in which the first set of input values are provided. Modifications to the default procedure are received. Using the modifications, a final procedure with a second set of input values provided in a sequence is generated. The GUI is tested with the final procedure. Testing the GUI includes providing the second set of input values to respective GUI components in the second sequence.

Abstract: Coated probe tips are described for plunger pins of an integrated circuit package tests system. One example has a plunger having a tip to contact a solder ball of an integrated circuit package, a sleeve to hold the plunger and allow the plunger to move toward and away from the package, the sleeve being held in a socket, a spring within the sleeve to drive the plunger toward the package, and a coating over the tip, the coating being harder than a solder ball.

Abstract: A second one-way clutch for a dual-bearing reel includes a ratchet wheel, a pawl member, and a pawl pivot controller. The ratchet wheel includes a plurality of ratchet teeth disposed in the circumferential direction at intervals of the ratchet wheel. The ratchet wheel is rotatable in conjunction with the drive shaft. The pawl member is pivotally disposed on the pivot shaft between an engagement position in which the pawl member engages the ratchet teeth and an un-engagement position in which the pawl member is un-engagement from the ratchet teeth. The pawl pivot controller is rotatably disposed on the pivot shaft, has an interlocking gear that rotates in response to the rotation of the drive shaft, and pivots the pawl member to the engagement position and the un-engagement position in response to the rotational direction of the interlocking gear.

Abstract: A method for fabricating substrate of a semiconductor device includes the steps of: providing a first silicon layer; forming a dielectric layer on the first silicon layer; bonding a second silicon layer to the dielectric layer; removing part of the second silicon layer and part of the dielectric layer to define a first region and a second region on the first silicon layer, wherein the remaining of the second silicon layer and the dielectric layer are on the second region; and forming an epitaxial layer on the first region of the first silicon layer, wherein the epitaxial layer and the second silicon layer comprise same crystalline orientation.

Abstract: Die transport apparatus and methods are disclosed herein. In some embodiments, a die transport apparatus may include: a plurality of regularly arranged adhesive areas, wherein individual adhesive areas have a die contact surface; and a relief area recessed from the die contact surfaces. Other embodiments may be disclosed and/or claimed.

Abstract: A method for fabricating substrate of a semiconductor device is disclosed. The method includes the steps of: providing a first silicon layer; forming a dielectric layer on the first silicon layer; bonding a second silicon layer to the dielectric layer; removing part of the second silicon layer and part of the dielectric layer to define a first region and a second region on the first silicon layer, wherein the remaining of the second silicon layer and the dielectric layer are on the second region; and forming an epitaxial layer on the first region of the first silicon layer, wherein the epitaxial layer and the second silicon layer comprise same crystalline orientation.

Abstract: An improved process for converting an oil suspension of nanoparticles (NPs) into a water suspension of NPs, wherein water, surfactant and a non-surfactant salt is used instead of merely water and surfactant, leading to greatly improved NP aqueous suspensions.

Abstract: A fin shaped structure and a method of forming the same. The method includes providing a substrate having a first fin structure and a second fin structure. Next, an insulation material layer is formed on the substrate. Then, a portion of the first fin structure is removed, to form a first recess. Following this, a first buffer layer and a first channel layer are formed sequentially in the first recess. Next, a portion of the second fin structure is removed, to form a second recess. Then, a second buffer layer and a second channel layer are formed in the second recess sequentially, wherein the second buffer layer is different from the first buffer layer.

Abstract: An improved process for converting an oil suspension of nanoparticles (NPs) into a water suspension of NPs, wherein water and surfactant and a non-surfactant salt is used instead of merely water and surfactant, leading to greatly improved NP aqueous suspensions.

Abstract: A present handle assembly is mounted to a handle shaft of a fishing reel. The handle assembly includes a handle arm and a handle knob. The handle arm is mounted to the handle shaft. The handle knob is mounted to the handle arm. The handle arm herein includes an arm body made of metal and a resin portion. The metallic arm body has a mount part and an arm part. The mount part is mounted to the handle shaft. The arm part is integrally formed with the mount part. The resin portion covers the mount part and at least a part of the arm part.

Abstract: A P-type field effect transistor includes: a gate area; an insulated area, adjacent to the gate area; a source region and a drain region made by silicon germanium, respectively, adjacent to the second side of the insulated area; a channel area, adjacent to the insulated area and formed between the source region and the drain region; a conductive layer, electrically connected to the source region and the drain region, respectively; and a plurality of capping layers, connected between the conductive layer and the source/drain regions, wherein the silicon layer(s) and the silicon germanium layer(s) are stacked alternately, and of which a silicon layer contacts the source/drain silicon germanium regions, while a silicon germanium layer contacts the conductive layer. The present invention also provides a complementary metal oxide semiconductor transistor including the P-type field effect transistor mentioned above.

Abstract: A method for fabricating substrate of a semiconductor device is disclosed. The method includes the steps of: providing a first silicon layer; forming a dielectric layer on the first silicon layer; bonding a second silicon layer to the dielectric layer; removing part of the second silicon layer and part of the dielectric layer to define a first region and a second region on the first silicon layer, wherein the remaining of the second silicon layer and the dielectric layer are on the second region; and forming an epitaxial layer on the first region of the first silicon layer, wherein the epitaxial layer and the second silicon layer comprise same crystalline orientation.

Abstract: A P-type field effect transistor includes: a gate area; an insulated area, adjacent to the gate area; a source region and a drain region made by silicon germanium, respectively, adjacent to the second side of the insulated area; a channel area, adjacent to the insulated area and formed between the source region and the drain region; a conductive layer, electrically connected to the source region and the drain region, respectively; and a plurality of capping layers, connected between the conductive layer and the source/drain regions, wherein the silicon layer(s) and the silicon germanium layer(s) are stacked alternately, and of which a silicon layer contacts the source/drain silicon germanium regions, while a silicon germanium layer contacts the conductive layer. The present invention also provides a complementary metal oxide semiconductor transistor including the P-type field effect transistor mentioned above.

Abstract: A method of characterizing a device may be used to determine a metal work function of the device according to a threshold voltage, a body effect, and an oxide capacitance of the device. The threshold voltage may be determined according to a current to voltage curve. The oxide capacitance may be determined according to a capacitor to voltage curve.

Abstract: A method and apparatus for power delivery network (PDN) analysis comprises obtaining time-domain single-pulse current response of the PDN, computing a maximum transient simultaneous switching noise (SSN) of the PDN according to the time-domain single-pulse current response, and determining that noise performance of the PDN conforms to a design requirement of the PDN if the maximum transient SSN is less than a PDN SSN threshold. Transient characteristics of the PDN can be analyzed.

Abstract: A second one-way clutch for a dual-bearing reel includes a ratchet wheel, a pawl member, and a pawl pivot controller. The ratchet wheel includes a plurality of ratchet teeth disposed in the circumferential direction at intervals of the ratchet wheel. The ratchet wheel is rotatable in conjunction with the drive shaft. The pawl member is pivotally disposed on the pivot shaft between an engagement position in which the pawl member engages the ratchet teeth and an un-engagement position in which the pawl member is un-engagement from the ratchet teeth. The pawl pivot controller is rotatably disposed on the pivot shaft, has an interlocking gear that rotates in response to the rotation of the drive shaft, and pivots the pawl member to the engagement position and the un-engagement position in response to the rotational direction of the interlocking gear.

Abstract: Disclosed is an uninterruptible power supply, including a rectifier for generating a DC voltage; an energy storage unit; an inverter for converting the DC voltage into a three-phase modulating voltage; a filter; a bypass switch circuit for selectively outputting a three-phase AC voltage or the three-phase modulating voltage as a three-phase load voltage; and a control circuit for controlling the operation of the uninterruptible power supply. The control circuit may use a flux compensation block with different operating modes to adjust the three-phase load voltage at the startup phase of a second inductive load and at the stable phase of the second inductive load, thereby compensating or correcting the flux of the second inductive load to prevent the flux distribution of the second inductive load from being saturated.

Abstract: Embodiments of present invention include a method and apparatus of estimating power supply of a 3D IC. The method particularly includes obtaining current information and layout information of circuit modules contained in a specific region of the 3D IC, gridding the specific region so as to form at least one three-dimensional grid having a plurality of side edges along chip stacking direction of the 3D IC, determining current of at least one of the plurality of side edges based on the current information and layout information of the circuit modules, and estimating power supply of the 3D IC based on the current of the at least one side edge. With the method and apparatus embodiments of the invention, power supply of a 3D IC may be effectively estimated and analyzed.

Abstract: A method and apparatus for power delivery network (PDN) analysis comprises obtaining time-domain single-pulse current response of the PDN, computing a maximum transient simultaneous switching noise (SSN) of the PDN according to the time-domain single-pulse current response, and determining that noise performance of the PDN conforms to a design requirement of the PDN if the maximum transient SSN is less than a PDN SSN threshold. Transient characteristics of the PDN can be analyzed.

Abstract: Methods and systems for data management are disclosed. With embodiments of the present disclosure, data files originating from the same source data can be de-duplicated. One such method comprises calculating one or more of a first characteristic value for first data in a first format, and one or more second characteristic values for one or more data in one or more second formats into which the first data can be converted, said characteristic value uniquely representing an arrangement characteristic of at least part of bits of data in a particular format. The method also includes storing one of the first data and the second data in response to one of the calculated characteristic values being the same as a stored characteristic value corresponding to a second data.